ST STM32F31xx

Digital-to-analog converter (DAC)
UM1581
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DocID023800 Rev 1
7 Digital-to-analog converter (DAC)
7.1 DAC Firmware driver registers structures
7.1.1 DAC_TypeDef
DAC_TypeDef is defined in the stm32f30x.h
Data Fields
 __IO uint32_t CR
 __IO uint32_t SWTRIGR
 __IO uint32_t DHR12R1
 __IO uint32_t DHR12L1
 __IO uint32_t DHR8R1
 __IO uint32_t DHR12R2
 __IO uint32_t DHR12L2
 __IO uint32_t DHR8R2
 __IO uint32_t DHR12RD
 __IO uint32_t DHR12LD
 __IO uint32_t DHR8RD
 __IO uint32_t DOR1
 __IO uint32_t DOR2
 __IO uint32_t SR
Field Documentation
 __IO uint32_t DAC_TypeDef::CR
 DAC control register, Address offset: 0x00
 __IO uint32_t DAC_TypeDef::SWTRIGR
 DAC software trigger register, Address offset: 0x04
 __IO uint32_t DAC_TypeDef::DHR12R1
 DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08
 __IO uint32_t DAC_TypeDef::DHR12L1
 DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C
 __IO uint32_t DAC_TypeDef::DHR8R1
 DAC channel1 8-bit right aligned data holding register, Address offset: 0x10
 __IO uint32_t DAC_TypeDef::DHR12R2
 DAC channel2 12-bit right aligned data holding register, Address offset: 0x14
 __IO uint32_t DAC_TypeDef::DHR12L2
 DAC channel2 12-bit left aligned data holding register, Address offset: 0x18
 __IO uint32_t DAC_TypeDef::DHR8R2
 DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C
 __IO uint32_t DAC_TypeDef::DHR12RD
 Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20
 __IO uint32_t DAC_TypeDef::DHR12LD
 DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24
 __IO uint32_t DAC_TypeDef::DHR8RD
 DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28