External interrupt/event controller (EXTI)
10 External interrupt/event controller (EXTI)
10.1 EXTI Firmware driver registers structures
10.1.1 EXTI_TypeDef
EXTI_TypeDef is defined in the stm32f30x.h
Data Fields
ï‚· __IO uint32_t IMR
ï‚· __IO uint32_t EMR
ï‚· __IO uint32_t RTSR
ï‚· __IO uint32_t FTSR
ï‚· __IO uint32_t SWIER
ï‚· __IO uint32_t PR
ï‚· uint32_t RESERVED1
ï‚· uint32_t RESERVED2
ï‚· __IO uint32_t IMR2
ï‚· __IO uint32_t EMR2
ï‚· __IO uint32_t RTSR2
ï‚· __IO uint32_t FTSR2
ï‚· __IO uint32_t SWIER2
ï‚· __IO uint32_t PR2
Field Documentation
ï‚· __IO uint32_t EXTI_TypeDef::IMR
ï€ EXTI Interrupt mask register, Address offset: 0x00
ï‚· __IO uint32_t EXTI_TypeDef::EMR
ï€ EXTI Event mask register, Address offset: 0x04
ï‚· __IO uint32_t EXTI_TypeDef::RTSR
ï€ EXTI Rising trigger selection register, Address offset: 0x08
ï‚· __IO uint32_t EXTI_TypeDef::FTSR
ï€ EXTI Falling trigger selection register, Address offset: 0x0C
ï‚· __IO uint32_t EXTI_TypeDef::SWIER
ï€ EXTI Software interrupt event register, Address offset: 0x10
ï‚· __IO uint32_t EXTI_TypeDef::PR
ï€ EXTI Pending register, Address offset: 0x14
ï‚· uint32_t EXTI_TypeDef::RESERVED1
ï€ Reserved, 0x18
ï‚· uint32_t EXTI_TypeDef::RESERVED2
ï€ Reserved, 0x1C
ï‚· __IO uint32_t EXTI_TypeDef::IMR2
ï€ EXTI Interrupt mask register, Address offset: 0x20
ï‚· __IO uint32_t EXTI_TypeDef::EMR2
ï€ EXTI Event mask register, Address offset: 0x24
ï‚· __IO uint32_t EXTI_TypeDef::RTSR2
ï€ EXTI Rising trigger selection register, Address offset: 0x28