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DMA controller (DMA)

UM1581

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DocID023800 Rev 1

9 DMA controller (DMA)

9.1 DMA Firmware driver registers structures

9.1.1 DMA_Channel_TypeDef

DMA_Channel_TypeDef is defined in the stm32f30x.h

Data Fields

 __IO uint32_t CCR

 __IO uint32_t CNDTR

 __IO uint32_t CPAR

 __IO uint32_t CMAR

Field Documentation

 __IO uint32_t DMA_Channel_TypeDef::CCR

 DMA channel x configuration register

 __IO uint32_t DMA_Channel_TypeDef::CNDTR

 DMA channel x number of data register

 __IO uint32_t DMA_Channel_TypeDef::CPAR

 DMA channel x peripheral address register

 __IO uint32_t DMA_Channel_TypeDef::CMAR

 DMA channel x memory address register

9.1.2 DMA_TypeDef

DMA_TypeDef is defined in the stm32f30x.h

Data Fields

 __IO uint32_t ISR

 __IO uint32_t IFCR

Field Documentation

 __IO uint32_t DMA_TypeDef::ISR

 DMA interrupt status register, Address offset: 0x00

 __IO uint32_t DMA_TypeDef::IFCR

 DMA interrupt clear flag register, Address offset: 0x04

9.1.3 DMA_InitTypeDef

DMA_InitTypeDef is defined in the stm32f30x_dma.h

ST STM32F31xx User Manual

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