ST STM32F31xx User Manual

UM1581
Window watchdog (WWDG)
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24 Window watchdog (WWDG)
24.1 WWDG Firmware driver registers structures
24.1.1 WWDG_TypeDef
WWDG_TypeDef is defined in the stm32f30x.h
Data Fields
 __IO uint32_t CR
 __IO uint32_t CFR
 __IO uint32_t SR
Field Documentation
 __IO uint32_t WWDG_TypeDef::CR
 WWDG Control register, Address offset: 0x00
 __IO uint32_t WWDG_TypeDef::CFR
 WWDG Configuration register, Address offset: 0x04
 __IO uint32_t WWDG_TypeDef::SR
 WWDG Status register, Address offset: 0x08
24.2 WWDG Firmware driver API description
The following section lists the various functions of the WWDG library.
24.2.1 WWDG features
Once enabled the WWDG generates a system reset on expiry of a programmed time
period, unless the program refreshes the counter (downcounter) before to reach 0x3F
value (i.e. a reset is generated when the counter value rolls over from 0x40 to 0x3F).
An MCU reset is also generated if the counter value is refreshed before the counter has
reached the refresh window value. This implies that the counter must be refreshed in a
limited window.
Once enabled the WWDG cannot be disabled except by a system reset.
WWDGRST flag in RCC_CSR register can be used to inform when a WWDG reset occurs.
The WWDG counter input clock is derived from the APB clock divided by a programmable
prescaler.
WWDG counter clock = PCLK1 / Prescaler.
WWDG timeout = (WWDG counter clock) * (counter value).
Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.

ST STM32F31xx Specifications

General

Brand	ST
Model	STM32F31xx
Category	Microcontrollers
Language	English