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Independent watchdog (IWDG)

UM1581

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DocID023800 Rev 1

14 Independent watchdog (IWDG)

14.1 IWDG Firmware driver registers structures

14.1.1 IWDG_TypeDef

IWDG_TypeDef is defined in the stm32f30x.h

Data Fields

 __IO uint32_t KR

 __IO uint32_t PR

 __IO uint32_t RLR

 __IO uint32_t SR

 __IO uint32_t WINR

Field Documentation

 __IO uint32_t IWDG_TypeDef::KR

 IWDG Key register, Address offset: 0x00

 __IO uint32_t IWDG_TypeDef::PR

 IWDG Prescaler register, Address offset: 0x04

 __IO uint32_t IWDG_TypeDef::RLR

 IWDG Reload register, Address offset: 0x08

 __IO uint32_t IWDG_TypeDef::SR

 IWDG Status register, Address offset: 0x0C

 __IO uint32_t IWDG_TypeDef::WINR

 IWDG Window register, Address offset: 0x10

14.2 IWDG Firmware driver API description

The following section lists the various functions of the IWDG library.

14.2.1 IWDG features

The IWDG can be started by either software or hardware (configurable through option

byte).

The IWDG is clocked by its own dedicated low-speed clock (LSI) and thus stays active

even if the main clock fails. Once the IWDG is started, the LSI is forced ON and cannot be

disabled (LSI cannot be disabled too), and the counter starts counting down from the reset

value of 0xFFF. When it reaches the end of count value (0x000) a system reset is

generated. The IWDG counter should be reloaded at regular intervals to prevent an MCU

reset.

The IWDG is implemented in the VDD voltage domain that is still functional in STOP and

STANDBY mode (IWDG reset can wake-up from STANDBY).

IWDGRST flag in RCC_CSR register can be used to inform when a IWDG reset occurs.

ST STM32F31xx User Manual

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