Tegam 1750 - Page 48

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5-7
PROGRAMMING AND INTERFACING
Connector J8 Timing Diagrams
Timing Diagram for Relay Outputs
NOTES: Approximately 5.5 m
s after a valid TTL output is generated, a valid output state may be read from
the HI, LO, GO
relay output contacts.
10 ms minimum
active low output
Reading Done Pulse
4 ms
1750 Read
Valid TTL Output
Valid Relay Output
approximately 6 ms delay for relay
contacts
Trigger In
Trigger Out
TTL Outputs
High
-Go-Low
Relay Outputs
Hi
-Lo-Go