Circuit Descriptions
1502C MTDR Service Manual
5–37
The function of the controller is to read bit pattern data from the display memory
and format it. This data is then sent (along with control and timing signals) to the
column and row drivers, which drive the LCD to provide the pattern on the display.
The row driver requires a start pulse at the beginning of each frame, 64 latch pulses
following that to scan the start pulse down the rows, and a framing signal to generate
the AC select voltage. These signals are generated by the controller as shown in the
row driver timing diagram (Figure 5–18).
The controller, running at a clock rate of 0.625 MHz, generates ST, LP, and FR with
the following periods:
ST 8 ms
LP 125
m
s
FR 16 ms
NOTE. The manufacturer’s nomenclature on the controller differs somewhat: ST =
FRP, LP = LIP, and FR = FRMB.
Thee column drivers require more control and timing signals than the row driver.
These include: E
IN
, E
CLK
, XSCL, D3 – D0, LP, and FR.
E
IN
is required at the start of every line to enable the first (leftmost, as seen from the
front of the display) column driver pair.
E
CLK
is required once to latch in E
IN
and three times after that to enable the
successive column driver pairs. Each successive E
CLK
must occur every 16 XSCL
pulses (i.e., after each column driver pair is full of 64 bits (4 X 16 bits)).
XSCL is required 16 times per column driver pair per line to shift in the bit pattern
data. Therefore, a total of 64 XSCL are required per line for the four column driver
pairs.
XSCL is generated by U3030, a counter clocked by CLP or LP from the controller.
It must be generated as such because the controller was designed to use with
80-channel column drivers instead of 64-channel column drivers. The controller
version of E
CLK
, CE0, is generated every 20 XSCL pulses rather than every 16
XSCL pulses as required by the 64-channel column drivers. The counter is used to
translate XSCL into E
CLK
.
As a consequence of generating E
CLK
as above, E
IN
must also be generated. This
is done with the U3065 flip-flop pair. The flip-flop pair is set when LP and LE0 are
asserted and hold set until XSCL (CLP) shifts in a logic 0 after the pulse. E
IN
is held
high for a duration long enough to enable the first column driver pair.
Row Driver Interface
Column Driver Interface
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