Circuit Descriptions
5–22
1502C MTDR Service Manual
Voltage comparator Q7021 is biased at 2 mA by dual transistor Q5020. During the
linearly rising ramp voltage, it compares the ramp to a programmed DC sample
reference voltage produced by the timebase DAC circuit. When the ramp reaches
the sample reference value, Q7021A rapidly turns on to produce a negative-going
signal across R7024. This pulse is coupled through C7022 and R7021 to turn on
Q6020, providing a positive pulse to the base of Q7020. The negative-going sampler
strobe coming from Q7020 is supplied to the sampler and to TP7010.
Timebase DAC U4020 and amplifier U5010 inverts and multiplies V
REF
by the
14-bit digital word loaded by the processor. It is filtered for noise by R7026 and
C5023 and connected to comparator Q7021 through R7027 to set the analog delay
(0 to 50 ns).
To calibrate the analog delay to 50 ns, the processor sets IR2
(IR2 high) and loads
a new 12-bit word in latches U3021 and U3022 (max 1-bit change per sweep) with
chip selects CS11
and CS12. DAC U3023 multiplies the reference current (1 mA
set by R3020) by the digital word from the latches. The DAC output current and
the current from the last two LSBs (which comes from the latches through R3031,
R3033, R3039, and R4020) are summed by U4021A and forced through R4021.
This develops a correction voltage at TP4020 of
"
5 VDC and a sensitivity of
2.5 mV per bit (the currents from the LSBs have been complimented by the
processor to correct their phase). The DAC circuit is designed to nominally run at
half of full dynamic range (2048/4096) of 2 mA, that generate 1 mA of current at
the summing node. That current is balanced out by 1 mA of current from R4020,
giving a nominal output of zero volts at TP4020 and TP4021.
U5020, R5020, R5021, and C5021 scale the correction signal (up to
"
5 VDC) at
TP4020 to
"
0.4 VDC at V
REF
of U4020. Resistors R5023 and R5022 furnish a
current to offset V
REF
to a –4 VDC
"
0.4 VDC (equivalent to
"
5 ns) correction
signal to the 50 ns analog delay.
To calibrate, the zero-distance delay (IR2
) is set low, and through R3037 and
CR3030, turns on Q3030, whose collector (through R3036 and R3035) raises the
cathode of CR4030 to +6 VDC. This allows R4023 to turn on Q4030. Capacitor
C4022, through R4030 and Q4030, is charged to the new corrected level at TP4020
that was asked for by the processor. The correction voltage on C4022 from buffer
amplifier U4021B is scaled by voltage divider R8023, R8022, and R8021 from a
range of
"
5 VDC to a range of zero to 3.5 VDC. This voltage is applied to the base
of comparator Q8020B, which provides
"
10 ns of zero-distance delay adjustment.
Components C3048, R3042, R2032, C3047, R2034, and C8024 are used to reduce
jitter and cross-coupling between circuits.
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