Tektronix 1502C - Page 9

Contents
iv
1502C MTDR Service Manual
Figure 2–1: Start-up Measurement Display 2–2. . . . . . . . . . . . . . . . . . . .
Figure 2–2: Measurement Display with 3-foot Cable 2–2. . . . . . . . . . . .
Figure 2–3: Cursor at End of 3-foot Cable 2–3. . . . . . . . . . . . . . . . . . . . .
Figure 2–4: Flat-Line Display Out to 50,000+ Feet 2–3. . . . . . . . . . . . . .
Figure 2–5: Flat-Line Display at –2.000 ft 2–4. . . . . . . . . . . . . . . . . . . . .
Figure 2–6: Waveform Off the Top of the Display 2–4. . . . . . . . . . . . . . .
Figure 2–7: Waveform at the Bottom of the Display 2–5. . . . . . . . . . . . .
Figure 2–8: Waveform with Gain at 5.00 m r /div 2–5. . . . . . . . . . . . . . .
Figure 2–9: Top of Pulse on Center Graticule 2–7. . . . . . . . . . . . . . . . . .
Figure 2–10: Rising Edge of Incident Pulse in Left-most
Major Division 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–11: Waveform Centered, Cursor at 0.000 ft 2–8. . . . . . . . . . . . .
Figure 2–12: Pulse Centered on Display 2–8. . . . . . . . . . . . . . . . . . . . . . .
Figure 2–13: Cursor on Lowest Major Graticule that Rising
Edge Crosses 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–14: Cursor on Highest Major Graticule that Rising
Edge Crosses 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–15: Jitter Apparent on Leading Edge of Incident Pulse 2–10. . . .
Figure 2–16: Jitter Captured Using Max Hold 2–10. . . . . . . . . . . . . . . . . . .
Figure 5–1: System Block Diagram 5–2. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–2: Waveform Accumulation Diagram 5–3. . . . . . . . . . . . . . . . .
Figure 5–3: Power Supply Block Diagram 5–4. . . . . . . . . . . . . . . . . . . . .
Figure 5–4: Processor Block Diagram 5–8. . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–5: Option Port Interface Block Diagram 5–11. . . . . . . . . . . . . . .
Figure 5–6: Video Processor Block Diagram 5–13. . . . . . . . . . . . . . . . . . .
Figure 5–7: Video Processor Output 5–15. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–8: Timebase Block Diagram 5–16. . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–9: Timebase Control 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–10: Combined Effects of Time Delay 5–18. . . . . . . . . . . . . . . . . .
Figure 5–11: Calibration of Delay Zero and 50-ns Analog Delay 5–19. . . .
Figure 5–12: Driver/Sampler Block Diagram 5–24. . . . . . . . . . . . . . . . . . .
Figure 5–13: Front Panel Block Diagram 5–26. . . . . . . . . . . . . . . . . . . . . . .
Figure 5–14: Display Module Block Diagram 5–29. . . . . . . . . . . . . . . . . . .
Figure 5–15: SBE Cell 5–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–16: Row Driver Block Diagram 5–31. . . . . . . . . . . . . . . . . . . . . .
Figure 5–17: Column Driver Block Diagram 5–32. . . . . . . . . . . . . . . . . . . .
Figure 5–18: Row Timing Diagram 5–33. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5–19: Column Timing Diagram 5–35. . . . . . . . . . . . . . . . . . . . . . . .
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