Theory of Operation—2230 Service
Common-base transistors, Q2101 and Q2102 form a
differential amplifier that presents a low-impedance load
for the Channel Switch. Offset is adjusted (using poten
tiometer R2138) to match the store display with the non
store display. Thermistor RT2131 temperature compen
sates the offset. Output current from the collector of
Q2102 is applied to the base of Q2103, a shunt-feedback
inverting amplifier. The inverted output signal voltage is
developed across R2146 in the collector circuit. The output
signal of Q2101 is developed across R2147 in series with
the signal at the collector of Q2103 to produce a single-
ended replica of the differential input signal at the base of
Q2105. Transistor Q2104 and its associated biasing resis
tors provide a constant-current bias source for Q2101,
Q2102, and Q2103.
Emitter-followers Q2105 and Q2106 provide the neces
sary signal drive and impedance matching to the Sample-
and-Hold diode bridge. Transistors Q2150 and Q2107 and
associated circuitry clamp the signal level to —2.5 V and
+1 V respectively at the sample and hold input.
Sample-and-Hold
A sampling diode bridge formed by CR2203 is biased
on by a strobe from the Strobe Generator. The bridge is
biased off during the hold period while the Analog-to-
Digital Converter (ADC) is converting the last sample.
When the bridge is strobed on, Hold capacitor C2235 is
charged to the new analog level present at the input to the
bridge. The bridge becomes biased off when the strobe
passes, and the voltage on the hold capacitor is held until
the next sample is taken. Signal samples are buffered by a
high-impedance input FET amplifier and coupled to the
ADC via an emitter-follower amplifier that provides the
input of the ADC with a low-impedance source. FET
Q2209B, with its source and gate connected together,
supplies source current to O2209A. A constant-current
load for the emitter-follower is provided by Q2211 and its
associated biasing resistors.
Strobe Generator
The ECL (Emitter-Coupled Logic) circuit formed by
U2203A, B, and C produces two pairs of complementary
control signals. One pair drives the sample strobe circuit to
bias the sampling diode bridge on, and the other clocks
the ADC. The 20 MHz ADCLK clock from the Clock Gen
erator circuit (Diagram 18, Digital Timebase) is shifted to
ECL levels by the voltage divider formed by R2265,
R2266, and R2267. Capacitor C2224 improves the high-
frequency characteristics of the divider string, and R2268
limits the input current to U2203C. OR/NOR-gate U2203C
produces the complementary ECL clocks to the ADC.
The sample-bridge strobe pulse is developed from the
ADC clock signals by U2203B, U2203A, and the RC circuit
composed of R2270 and C2225. The uninverted output of
U2203C (CLK A/D) is applied to pin 4 of OR/NOR-gate
U2203A where its signal transitions are seen immediately.
The inverted output of U2203C (CLK A/D) must charge
C2225 (through R2270) to the switching threshold of
U2203B before U2203B can switch state and change the
state of input pin 5 of U2203A. When a HI-to-LO transition
occurs on pin 4 of U2203A, the output at pin 3 goes HI
and pin 2 goes LO to follow the input signal. A short time
later, the charge on C2225 reaches the switching thresh
old of OR-gate U2203B, and the output of that gate goes
HI. That HI switches the output at pin 3 of U2203A back
LO and pin 2 back HI. The total duration of the pulse is
approximately 10 ns. Pin 4 of U2203A switches from LO
to HI on the next transition of ADCLK, and after a short
delay the output of U2203B goes LO again, readying the
circuit for the next pulse.
The complementary sample strobes are applied to
opposite bases of a current-mode switch formed by Q2208
and Q2207. The amplified output is coupled to the sam
pling diode bridge biasing circuit by T2201 and T2202, a
common mode transformer. Transformer coupling prevents
any dc offsets from entering the bridge via the biasing cir
cuit by completely isolating the bias voltage from the signal
voltage. The ECL output lines are terminated by R2278
and R2277 at the differential switch. The resistors match
the characteristic impedance of the transmission path to
prevent reflections that occur when the signals are not
properly terminated. Common mode transformers T2202
and T2203 improve the symmetry of the strobe pulses so
that, when the pulses are combined at CR2203, the pulses
will cancel each other out and not show up as noise in the
signal.
When the sample strobe is being amplified, the polarity
of the pulse on pin 6 of T2201 is positive. The sampling
strobe path is through C2229, C2230, and T2203 to for
ward bias CR2203. Signal current then flows through the
forward biased diodes to charge Hold capacitor C2235. At
the end of the strobe the polarity changes across pins 6
and 1 of T2201. The voltage on C2229 and C2230
increase the reverse bias on the bridge during the off time.
R2281 and the duty cycle of the strobe determine the
charge on C2229 and C2230.
Analog-to-Digital Converter
Analog-to-Digital Converter U2204, converts analog
input voltages in the range of 0 V to —2 V into 8-bit digital
representations. The digital output code for 0 V is
11111111 and 00000000 for - 2 V. Conversions are con
tinually taking place at 20 Megasamples per second (the
ADCLK rate) regardless of the SAVECLK rate. The ADC is
3-29
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