Theory of Operation— 2230 Service
Another section of the circuitry is used in conjunction
with the Min-Max Sampling mode to determine whether
the last sample clocked into the MIN/MAX Registers was
a NEWMIN or a NEWMAX. This knowledge is necessary
in chopped Min/Max mode to place the Min and Max data
samples into the Acquisition Memory in the correct order.
Each Swap Register consists of two sets of two. The Min
data is placed in both buffers of one set and the Max data
in both buffers of the other set at the same time by the ris
ing edge of BUFFERCLK. The outputs of one of the
buffers in each set are connected to one of the memory
data buses and the other half of the buffers are connected
to the opposite memory data bus. Depending on which
buffer in each set is enabled, the data is placed on the
memory data buses by either the nonswapping buffers or
the swapping buffers (controlled by enable signals SWAP
and SWAP).
When swapping is not enabled, as in sampling and X-Y
modes, the SWAPEN signal from the Acquisition Mode
Register (U3310) is LO, and flip-flop U3307B is held set.
NAND-gates U3313B and U3313A have as one of their
inputs the Q and Q outputs of the flip-flop respectively.
With the flip-flop held set, NAND-gate U3313B is enabled
to pass the DATAEN enabling signal to the nonswapping
buffers only. In chopped Min/Max mode, swapping is
enabled to place the Min and Max data in memory in the
correct order. The SWAPEN signal is set HI and the reset
is removed from flip-flop U3307B so that the latch circuit
on the D input controls the SWAP/SWAP states.
At initialization in Min/Max mode, both MINCLK and
MAXCLK (U3309) go HI for the first data byte. At the end
of the initialization pulse, both inputs to the latch are
removed by disabling the multiplexer outputs, and the out
put states of both NOR-gates (U3308C and U3308D)
remain LO.
A MAXCLK or MINCLK signal going HI is accompanied
by a LO on the opposite signal line. If the MINCLK signal
goes HI, the accompanying LO on the MAXCLK line
causes U3308C to change output state from LO to HI.
That HI goes to pin 12 of U3308D, holding its output LO.
No further switching of the latch occurs unless the
MAXCLK signal goes HI. MINCLK going HI again will not
cause any state changes in the latch. If MAXCLK goes HI,
U3308D will change to a LO output state, and U3308D
pin 13 will be latched HI. The state of pin 13 when the ris
ing edge of BUFFERCLK occurs is clocked through flip-
flop U3307B, enabling one of the NAND-gates that must
pass the DATAEN enabling signal to the Swap Registers.
If a NEWMAX (MAXCLK) occurred last, the Q output of
U3307B will be HI and SWAP will be LO, enabling the
nonswapping buffers, U3236 and U3239. If a NEWMIN
(MINCLK) occurred last, pin 13 of U3308D will be LO.
When that LO is clocked through U3307B, NAND-gate
U3313B goes LO, passing and inverting the DATAEN ena
bling signal. That makes SWAP LO, and the swapping
buffers (U3237 and U3238) are enabled, placing the Max
data into the Acquisition Memory that the processor looks
at to find the data that occurred last.
Acquisition Clock Decoder
The Acquisition Clock Decoder circuitry is composed of
three parts. One part is a flip-flop delay chain that pro
duces the transfer clocks. The output clocks from the
chain are essentially copies of the SAVECLK delayed by
successive CONV or OONV clock periods. The second
part controls acquisition writes by producing the
ACQWRITE and DATAEN clocks. The outputs of this por
tion switch control of the Acquisition Memory to the
acquisition memory system. This enables the data from
the Swap Registers onto the memory data buses so it can
be written into memory. The final section of the clock
decoder circuitry drives the analog Channel Switch to
select the vertical channel signal to be digitized.
DELAY CHAIN. The first four of five flip-flops in the
delay chain (U4104B, U3101A, U3101B, and U3103B) are
clocked by CONV for delays through each of either 100 ns
or 50 ns (10 MHz and 20 MHz CONV clock rates respec
tively). The various delays represented by the output clock
lets data being transferred through each device in the
acquisition pipeline settle at the outputs; and, in the case
of Min-Max mode, be processed through the comparators
before the next data byte is clocked in. The last flip-flop in
the delay chain (U3103A) is clocked by CONV and pro
duces a delay of one-half of a CONV-clock period between
EVENCLK (U3101B) and BUFFERCLK (U3103A). Every
rising edge of BUFFERCLK transfers both 8-bit data bytes
from the MIN/MAX Registers into the Swap Registers and,
in chopped Min-Max mode, clocks flip-flop U3307B in the
Swap-Control circuitry. Flip-flop U3307B latches the last
state of MINCLK and MAXCLK to determine which set of
Swap Registers are enabled to pass data to the Acquisi
tion Memory buses. See the “Acquisition Mode Control"
description for additional information on Swap Register
enabling.
ACQUISITION WRITE. Flip-flops U3105A and U3105B
form a self-resetting circuit that produces the ACQWRITE
signal once each SAVECLK period. The time duration of
ACQWRITE is one WRITECLK period, either 100 ns or
200 ns (twice the CONV clock period) except at the
fastest sampling rates when the SAVECLK is running at
10 MHz. In that case, once switched HI to write the first
data into memory, ACQWRITE remains HI until ENDREC
goes LO (a full record). The logic gating of U3104A, B, C,
and D controls the reset line to U3105B.
3-34
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