Tektronix 2230 Service Manual

Maintenance—2230 Service
measure the time between an asynchronous trigger (either
the A or the B Gate) and the acquisition systems master
clock. The timer divides the 50 ns convert clock (CONV)
into 200 time periods.
The CDT diagnostic checks the Clock Delay Timer cir
cuit using two self-triggered acquisitions. Each test
acquisition is started when the microprocessor sets CAL-
TIMER (U4247 pin 2) TRUE and TEST (U4228 pin 10) is
set first LO and then HI. When PREFULL (U4228 pin 2)
goes HI, U4127 pin 4 goes TRUE causing the charge cycle
of the CDT (C4201) to start. The discharge cycle begins
100 to 150 ns later when TRGD goes TRUE forward bias
ing Q4203.
The time that the voltage on C4201 is above the volt
age at U4229 pin 2 (set by R4214, R4215 and R4216) dur
ing the discharge cycle is proportional to the time
difference between U4127 pin 4 going HI and TRGD
(U4226 pin 9) going TRUE. This time is counted by U4230
(at the CONV clock rate) and U4231B. The MSB of the
CDT word (bit 8) is shared with BYTEINT (the hardware
flag signifying that a byte interrupt has occurred). This
shared bit is read by the microprocessor through U3428
pin 8.
If an error is found, one of the following messages is
displayed on the crt:
CDT : TIME-OUT <tb_mode_reg_pattern>
CDT : PRE-DETRIG <tb_mode_reg_pattern>
CDT : uncaled : min = <min_actual>
CDT : uncaled : delta = <delta_actual>
Where:
TIME-OUT is caused by not receiving a ENDREC
Tb_mode_reg_pattern is a 2-digit hexadecimal
value indicating the pattern used in the Time Base
Mode Register during the test acquisition.
PRE-DETRIG is caused by the CDT counter
overflowing (CNTCLR U4231 pin 6).
Tb mode reo pattern is a 2-digit hexadecimal
value indicating the pattern used in the Time Base
Mode Register during the test acquisition.
Min_actual is the value (85.0 to 115.0) read from
U4230 + CDT msb (U3428 pin 8) during a test
acquisition with TEST LO.
Delta_actual is the value (200 to 210) read from
U4230 + CDT msb (U3428 pin 8) during a test
acquisition with TEST HI minus the value of the pre
vious min cycle.
FP_A2D. This test checks the front panel A/D
converter circuitry. A conversion is done on three of the
analog inputs (A CURS, U6106 pin 12, B CURS, U6106
pin 13, and ground, U6108 pin 5). The algebraic sum of A
CURS and B CURS are checked. Their sum should be
between 0x100 and 0x700. Ground is also checked. It
should be between 0 and 5 front panel A/D converter
counts (5 — 1024 of VREF).
During power-up this test defines a variable
(FP_POLLED) that controls how the microprocessor
works with the front panel. If during testing a Ml is not
generated, it is assumed that the front panel will never
generate a Ml and the microprocessor must poll the front
panel to see when to transfer front-panel data.
If an error is found one of the following messages is
displayed on the crt:
NOTE
In firmware version 02, the Gnd message should be
FP_A2D: gnd = <actual> > 5 (greater than only)
FP_A2D : cursor :a= <actual> & b= <actual>
FP__A2D : gnd = <actual> < > 5
FP_A2D : TIME-OUT
Where:
Actual is a 3-digit hexadecimal number representing
the result of a front-panel digitization.
TIME-OUT indicates A/D INT FLAG (U6101D pin 13)
did not occur within 0x800 polls by the micro
processor.
CAL_AIDS. The instrument calibration aids are used to
help calibrate the instrument.
CAL_V_POS. This calibration aid is used to calibrate
the storage position control (see "Adjustment Procedure”).
CAL_CLK_DLY. Clock Delay Timer (CDT) calibration
uses a graphic display. The horizontal position of the
display cross hairs is attached to the min count and the
vertical position is attached to the delta count (see
"Adjustment Procedure”).
NOTE
Only BOX and OUT_PORTS is run by version 01
software.
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Tektronix 2230 Specifications

General

Brand	Tektronix
Model	2230
Category	Test Equipment
Language	English