2 CH 1 STATUS
TO<fb
P
+ CH 1 SIC
SI 12
| CH 1 PREAM? |
01E2, QI03
DIM, QMS
U130
NTRIC1 & PTRIG1
CH 2 ACQ
' SIGNALS
<$>
■POSITION SICNALS TO•
POSITION SIGNAL
CONDITIONING
(POSITION INTERFACE)
VERTICAL PREAMPS A
CHANNEL SWITCHING
s s s s
SSS0
NTRIC2 4 PTRIC2
CH
ADO
CH 1-SEL i
CH 2-SEL ,
VALT,
CHOP TOO
♦CH 2 SIG
ALT
CHOP
INVERT
[ CHANNEL |
SVITCH
LOGIC
US37A
U540A
U7221
U72023
CH 2 PREAMP |
0152, 0153
Old , 0165
l'!80
. CHOP I
2 CH 2 STATUS
^ * TO <
)<9>
CH 2
POSITION
R162
CHOP
OSCILLATOR
AND CHOP
BLANKING
|U540B, U537C
U537D
CHANNEL
SVITCH
CR200 , CR201
CR202 , CR203 |
U7202A
I DELAY LINE
DRIVER
0202 , 0203
Q203 , Q207 |
U225
VERT I CAL / \
OUTPUT < 3 >
AMPLIFIER^/
VERTICAL
| OUTPUT AMPL |
0230 , 0231
Q251 , 0255
Q2S6, 0257
A/B SVP SEP
Q283, 0284
0285
BW LIMIT
CR226 , CR227
CR228, CR229
ENA-STO/y
" FROM <1 S>
L 1
UV-OUT, DV-OUT.
TO/FROM V
A/B SVP SEP
BV LIMIT
R280
S226
HOR-REF
VAR
XY
CHOP BLANK
SWEEP INTERFACE
A13
U78BA, B, C, D
U781A, B, C, 0
U782A, B, C, D
U783A , B
S250
XY
1 CH I SELECTED
A18 SWEEP
REF BOARD
[ Q7501 ,075081
HOR-CAL ,
HOR-MAG ,
L * . HOR-REF,
HOR-VAR,
1K-REF, 4K-REF I
S721
HOR-REF
A SVP
HOR X 10
A ONLY
3 ONLY
HALT
ALTERNATE 01 SPLAY SVJTCHINC
UBS0E , U565C, U6708 , U680A , B
0882 , 0983 , 0684 , 0887
B TIMINC
SVITCH
AND RC
XI0 MAC
CONTROL
SEP
3 SVEEP LOGIC
I US6SA, B, F , U870A
U680C, D, 0830, Q631
B MILLER SVEEP
Q709 > Q710A, B
Q712
4a tor
B END OF SVEEP |
COMPARATOR
0843, U685D
X-AXIS,
J L
horizontal
R7281 POSITION]
A SVP
A DISP
BO ISP
B SVP
RUN AFTER DLY
US60D, Q837
B TIMING ANO
ALTERNATE B SVEEP
PROBE
ADJUST
Figure 9-4. Detailed Analog block diagram.