AIR FORCE T033A1
-13-496-1
NAVELEX
0969-LP-170-0010
Operation
Instructions
11
Pin
11,
X
Signal Input. A sample
of the
signal present in the CH 1 Preamplifier
is connected here.
When pin
12
is HI, the sweep inputs
from pins
9 and 10
are
internally disconnected
and the signal
from pin
1 1 is
amplified and connected
to
the
outputs on
pins 2 and 7.
12
Pin
12,
X-Y
Control.
This pin is set HI only
in
the
X-Y
mode. See pin 1
1
.
13
Pin
13,
Frequency
Compensation.
The fre-
quency compensating capacitor
is connected
here.
14 Pin
14,
Horizontal
Position
. The horizontal
POSITION
control is connected
here.
Changing
the dc volt-
age on this pin shifts
the
dc
level
of the
outputs
at
pins
2
and
7,
except in
the
X-Y
mode.
(7)
-t-A
GATE
OUT
Amplifier. The
+A GATE
OUT
Amplifier
consists of
02712 and
associated
circuitry.
The
A sweep
gate signal from
the
collector
of
02702 (part of
the
A trigger amplifier)
is
connected
to
the
base of
02712.
At
the
beginning
of A sweep
the sweep
gate
turns
off
02712, causing its
collector
to
go to
-^5
volts.
At the end of
A sweep
the sweep
gate
steps
positive,
turning
on
02712.
The
collector of
02712 goes
to about
0 volts.
The resultant
+A GATE
OUT signal
is
about
-^5
volts
while
an A sweep
ramp
is being
generated
and
about
0
volts the
rest
of the
time.
(8)
+B
GATE OUT
Buffer.
The +B
GATE OUT
Buf-
fer
consists
of
02696 and
associated
circuitry.
The
input
to
the
buffer circuit
is
obtained
from three
sources;
the partial
B
Gate signal
from
pin 10
of
U2690,
the
B
sweep
gate from
the collector
of 02602
which is part
of the B
trigger ampli-
fier, and
the delayed
gate signal
from pin 16 of U2790.
Figure
4-9
shows the
time
relationship of the
two signals.
The output
of the
Buffer is LO
only when
both input
signals
are LO. All
three
input signals are LO at
the
same
time
only
while
a
B
ramp is
being generated. The output
of the
Buffer is
supplied to
the
^B
GATE OUT
Amplifier
in the Main Module.
(9)
Sweep
Control.
Sweep
Control consists
of
U2750
and
associated
circuitry.
The circuit
controls
holdoff dura-
tion, AUTO
sweep,
and single
sweep
operation.
Figure
4-10
shows a
functional block
diagram of U2750
and
associated
circuitry.
(a) Holdoff
Control. Holdoff
control is provided
by
a
Miller ramp
generator which
consists of
three tran-
sistors within
U2750, and an RC
network. Resistors
R2776
and R2777 are the
timing resistors.
Capacitor
C2762 and
a
capacitor selected
by the A TIME/DIV
switch
are the
timing capacitors. Figure
4-10
shows
a functional
block
diagram
of U2750 and associated
circuitry.
Figure
4-1
1
shows
the waveforms
produced
by the
holdoff control
circuitry.
1^
At
the beginning
of A sweep generation,
pin
6 of U2750 steps
LO.
This
LO passes through an inverting
amplifier and
turns on transistor
C and turns off
transistors
D and
E
(see Figure 4-10).
When
transistors D and E
turn
off, pin
1
1
of U2750 is pulled
more
positive through
R2762. Pin
1 1 is clamped
at about
-)-5.7
volts
by
a
diode
within
U2750.
The
current through
the timing
resistors
(R2776 and R2777)
is supplied
by transistor
C through
pin
10 of U2750. This
condition is
maintained until
the end
of
A sweep generation.
2
At the end
of A sweep
generation, pin
12 of
U2750
momentarily
steps HI
which sets
the holdoff
latch
within
U2750. The Q
output of
the holdoff
latch goes
HI
causing pin
9 of U2750
to go HI. The
HI on pin
9 resets
and
holds off
the
A Trigger Generator.
3 When the
A Trigger Generator
resets (or
the
AUTO
sweep gate steps HI), pin
6
of
U2750
steps HI.
This
turns off transistor
C and turns on
transistors D and E
with-
in
U2750.
Pin
10 is pulled positive
to about -H .4 volts
through
R2776 and
R2777.
4 After transistor C
turns off, pin 10
tries
to
go
more
positive than
+1.4
volts.
This turns on
transistor
D
harder
and supplies current
through
C2762,
R2776,
and
R2777.
This current
holds pin 10
at
about
+1
.4 volts and
begins charging C2762.
As C2762
charges, pin 1 1
of
U2750
begins
going less positive.
5 As pin 1
1
of
U2750 goes less positive, the
diode selected by the
A
TIME/DIV
becomes forward
biased. Now
the current
to
hold
pin 10 at
+1.4
volts
is sup-
plied through
C2762 and
a
capacitor
selected
by
the
A
TIME/DIV.
Since
the voltage across
R2776 and R2777
doesn't change, the
current doesn't change.
Now this cur-
rent
must charge two
capacitors, and the voltage
ramp on
pin
1
1
of
U2750
will
not be
as
steep.
The ramp can
also
be made less steep
by increasing
the resistance of
the
A
TRIGGER
HOLDOFF
control (R2777).
6
When
the voltage
on pin 1
1
falls
to about
1
volt,
the R input of the
holdoff latch
within
U2750 is set
HI
through an
inverting amplifier.
The holdoff
latch
resets
and
its Q output
goes LO. When the
Q output
goes
LO, pin
9
of
U2750
goes LO and
terminates
holdoff.
(b)
AUTO
Sweep
Control.
When pin 4 of
U2750
is
set LO by the
TRIG MODE switch. Sweep
Control pro-
vides
a
baseline trace in the
absence of
an
adequate
trigger
signal.
Figure
4-10
shows
the Sweep Control integrated
circuit and associated
circuitry. Figure
4-12
shows the
waveforms produced during AUTO sweep gate
generation.
4-20
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