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USB Interrupts
21.4 USB Interrupts
There are three interrupt flag registers with associated interrupt-enable mask registers.
Table 21-1. USB Interrupt Flags Interrupt-Enable Mask Registers
Associated Interrupt
Interrupt Flag Description
Enable Mask Register
USBCIF
Contains flags for common USB interrupts
USBCIE
USBIIF
Contains interrupt flags for endpoint 0 and all the IN endpoints
USBIIE
USBOIF
Contains interrupt flags for all OUT endpoints
USBOIE
Note: All interrupts except SOF and suspend are initially enabled after reset.
The USB controller uses interrupt #6 for USB interrupts. This interrupt number is shared with Port 2 inputs;
hence, the interrupt routine must also handle Port 2 interrupts if they are enabled. For an interrupt request
to be generated, IEN2.P2IE must be set to 1 together with the desired interrupt enable bits from the
USBCIE, USBIIE, and USBOIE registers. When an interrupt request has been generated, the CPU starts
executing the ISR if there are no higher-priority interrupts pending. The interrupt routine should read all the
interrupt flag registers and take action depending on the status of the flags. The interrupt flag registers are
cleared when they are read, and the status of the individual interrupt flags should therefore be saved in
memory (typically in a local variable on the stack) to allow them to be accessed multiple times.
At the end of the ISR, after the interrupt flags have been read, the interrupt flags should be cleared to
allow for new USB and P2 interrupts to be detected. The Port 2 interrupt status flags in the P2IFG register
should be cleared prior to clearing IRCON2.P2IF.
When waking up from suspend (typically in PM1), the USB D+ interrupt flag, P2IFG.DPIF, is set. The D+
interrupt flag indicates that there has been a falling edge on the D+ USB data pin. This is a resume event.
21.5 Endpoint 0
Endpoint 0 (EP0) is a bidirectional control endpoint, and during the enumeration phase all communication
is performed across this endpoint. Before the USBADDR register has been set to a value other than 0, the
USB controller is only able to communicate through endpoint 0. Setting the USBADDR register to a value
between 1 and 127 brings the USB function out of the default state in the enumeration phase and into the
address state. All configured endpoints are then available for the application.
The EP0 FIFO is only used as either IN or OUT, and double buffering is not provided for endpoint 0. The
maximum packet size for endpoint 0 is fixed at 32 bytes.
Endpoint 0 is controlled through the USBCS0 register by setting the USBINDEX register to 0. The USBCNT0
register contains the number of bytes received.
21.6 Endpoint-0 Interrupts
The following events may generate an EP0 interrupt request:
• A data packet has been received (USBCS0.OUTPKT_RDY = 1)
• A data packet that was loaded into the EP0 FIFO has been sent to the USB host.
(USBCS0.INPKT_RDY should be set to 1 when a new packet is ready to be transferred. This bit is
cleared by hardware when the data packet has been sent.)
• An IN transaction has been completed (the interrupt is generated during the status stage of the
transaction).
• A STALL has been sent (USBCS0.SENT_STALL =
1)
• A control transfer ends due to a premature end-of-control transfer (USBCS0.SETUP_END = 1)
Any of these events causes USBIIF.EP0IF to be asserted, regardless of the status of the EP0 interrupt
mask bit USBIIE.EP0IE. If the EP0 interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.P2IF is
also asserted. An interrupt request is only generated if IEN2.P2IE and USBIIE.EP0IE are both set to 1.
193
SWRU191C–April 2009–Revised January 2012 USB Controller
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