X1/XCLKIN
SYSCLKOUT
Write to PLLCR
XCLKIN * 2
(Current
CPU Frequency)
XCLKIN/2
[CPU Frequency While PLL is Stabilizing
With the Desired Frequency.
This Period (PLL Lock-up Time, t )
is 131 072 XCLKIN Cycles Long.]
p
XCLKIN * 4
(Changed CPU Frequency)
(XCLKIN * 5)
t
h(XPLLDIS)
t
h(boot-mode)
(A)
XCLKIN
X1
XRS
XF/XPLLDIS
XMP/MC
Boot-Mode Pins
XCLKOUT
I/O Pins
Address/
Data/
Control
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Dependent
XCLKIN/8
User-Code Execution Phase
t
h(XMP/MC)
(Don’t Care)
(Don’t Care)
User-Code Dependent
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
XPLLDIS Sampling
(Don’t Care)
GPIOF14/XF
GPIOF14
Peripheral/GPIO Function
GPIO Pins as Input Peripheral/GPIO Function
(Don’t Care)
User-Code Execution
t
d(EX)
t
su(XPLLDIS)
t
w(RSL2)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T –APRIL 2001–REVISED MAY 2012
A. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN
cycles from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is
based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or
without PLL enabled.
Figure 6-13. Warm Reset in Microcomputer Mode
Figure 6-14. Effect of Writing Into PLLCR Register
Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 107
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