CLKX
FSX
DX
M30
M31
DR
M28
M24
M29
M25
LSB MSB
M32
M33
Bit 0
Bit(n-1)
(n-2) (n-3) (n-4)
Bit 0
(n-2) (n-3) (n-4)Bit(n-1)
TMS320F2810, TMS320F2811, TMS320F2812
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SPRS174T –APRIL 2001–REVISED MAY 2012
6.31.2 McBSP as SPI Master or Slave Timing
Table 6-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
(1)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M30 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 30 8P – 10 ns
M31 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 1 8P – 10 ns
M32 t
su(BFXL-CKXH)
Setup time, FSX low before CLKX high 8P + 10 ns
M33 t
c(CKX)
Cycle time, CLKX 2P 16P ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
(1)
MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M24 t
h(CKXL-FXL)
Hold time, FSX low after CLKX low 2P ns
M25 t
d(FXL-CKXH)
Delay time, FSX low to CLKX high P ns
Disable time, DX high impedance following last data bit
M28 t
dis(FXH-DXHZ)
6 6P + 6 ns
from FSX high
M29 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 153
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