TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012
www.ti.com
Table 3-13. PIE Configuration and Control Registers
(1)
NAME ADDRESS SIZE (x16) DESCRIPTION
PIECTRL 0x0000 0CE0 1 PIE, Control Register
PIEACK 0x0000 0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0000 0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0000 0CE3 1 PIE, INT1 Group Flag Register
PIEIER2 0x0000 0CE4 1 PIE, INT2 Group Enable Register
PIEIFR2 0x0000 0CE5 1 PIE, INT2 Group Flag Register
PIEIER3 0x0000 0CE6 1 PIE, INT3 Group Enable Register
PIEIFR3 0x0000 0CE7 1 PIE, INT3 Group Flag Register
PIEIER4 0x0000 0CE8 1 PIE, INT4 Group Enable Register
PIEIFR4 0x0000 0CE9 1 PIE, INT4 Group Flag Register
PIEIER5 0x0000 0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0000 0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0000 0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0000 0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0000 0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0000 0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0000 0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0000 0CF1 1 PIE, INT8 Group Flag Register
PIEIER9 0x0000 0CF2 1 PIE, INT9 Group Enable Register
PIEIFR9 0x0000 0CF3 1 PIE, INT9 Group Flag Register
PIEIER10 0x0000 0CF4 1 PIE, INT10 Group Enable Register
PIEIFR10 0x0000 0CF5 1 PIE, INT10 Group Flag Register
PIEIER11 0x0000 0CF6 1 PIE, INT11 Group Enable Register
PIEIFR11 0x0000 0CF7 1 PIE, INT11 Group Flag Register
PIEIER12 0x0000 0CF8 1 PIE, INT12 Group Enable Register
PIEIFR12 0x0000 0CF9 1 PIE, INT12 Group Flag Register
Reserved 0x0000 0CFA – 0x0000 0CFF 6 Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
46 Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated
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