Texas Instruments TMS320C2810 User Manual

22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
Data Valid
SPISOMI Data Is Valid
SPISTE
(A)
12
13
14
17
18
21
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com SPRS174T –APRIL 2001–REVISED MAY 2012
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
before the valid SPI clock edge and
remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-29. SPI Slave Mode External Timing (Clock Phase = 1)
Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 125
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Texas Instruments TMS320C2810 Specifications

General

Brand	Texas Instruments
Model	TMS320C2810
Category	Signal Processors
Language	English