CLKX
FSX
DX
DR
M54
M58
M56
M53
M55
M59
M57
LSB
MSB
M60
M61
Bit 0
Bit(n-1) (n-2) (n-3) (n-4)
Bit 0
Bit(n-1) (n-2) (n-3) (n-4)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012
www.ti.com
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
(1)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M58 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 30 8P – 10 ns
M59 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 1 8P – 10 ns
M60 t
su(FXL-CKXL)
Setup time, FSX low before CLKX low 16P + 10 ns
M61 t
c(CKX)
Cycle time, CLKX 2P 16P ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
(1)
MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M53 t
h(CKXH-FXL)
Hold time, FSX low after CLKX high P ns
M54 t
d(FXL-CKXL)
Delay time, FSX low to CLKX low 2P ns
M55 t
d(CLKXH-DXV)
Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns
Disable time, DX high impedance following last data bit
M56 t
dis(CKXH-DXHZ)
P + 6 7P + 6 ns
from CLKX high
M57 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Figure 6-48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
156 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated
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