EasyManuals Logo

Texas Instruments TMS320C2810 User Manual

Texas Instruments TMS320C2810
172 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #148 background image
Analog Input on
Channel Ax
Analog Input on
Channel Bv
ADC Clock
Sample and Hold
SH Pulse
t
SH
t
dschA0_n
t
dschB0_n
t
dschB0_n+1
Sample n
Sample n+1
Sample n+2
t
dschA0_n+1
t
d(SH)
ADC Event Trigger from EV
or Other Sources
SMODE Bit
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T APRIL 2001REVISED MAY 2012
www.ti.com
6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB),
software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions
on two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result
register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the
Result register update. The selected channels will be sampled simultaneously at the falling edge of the
Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum)
or 16 ADC clocks wide (maximum).
NOTE
In Simultaneous Mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, and so forth).
Figure 6-42. Simultaneous Sampling Mode Timing
Table 6-49. Simultaneous Sampling Mode Timing
AT 25-MHz
SAMPLE n SAMPLE n + 1 ADC CLOCK, REMARKS
t
c(ADCCLK)
= 40 ns
Delay time from event
t
d(SH)
2.5t
c(ADCCLK)
trigger to sampling
Sample/Hold width/ Acqps value = 0–15
t
SH
(1 + Acqps) * t
c(ADCCLK)
40 ns with Acqps = 0
Acquisition Width ADCTRL1[8:11]
Delay time for first
t
d(schA0_n)
result to appear in 4t
c(ADCCLK)
160 ns
Result register
Delay time for first
t
d(schB0_n)
result to appear in 5t
c(ADCCLK)
200 ns
Result register
Delay time for
successive results to
t
d(schA0_n+1)
(3 + Acqps) * t
c(ADCCLK)
120 ns
appear in Result
register
Delay time for
successive results to
t
d(schB0_n+1)
(3 + Acqps) * t
c(ADCCLK)
120 ns
appear in Result
register
148 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Texas Instruments TMS320C2810 and is the answer not in the manual?

Texas Instruments TMS320C2810 Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320C2810
CategorySignal Processors
LanguageEnglish

Related product manuals