Texas Instruments TMS320C2810 User Manual

9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
SPISTE
(A)
1
2
3
5
8
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com SPRS174T –APRIL 2001–REVISED MAY 2012
A. In the master mode, SPISTE goes active 0.5t
c(SPC)
before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5t
c(SPC)
after the receiving
edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-26. SPI Master Mode External Timing (Clock Phase = 0)
Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 119
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Texas Instruments TMS320C2810 Specifications

General

Brand	Texas Instruments
Model	TMS320C2810
Category	Signal Processors
Language	English