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Texas Instruments TMS320C2810 User Manual

Texas Instruments TMS320C2810
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XCLKOUT
(A)
TDIRx
t
w(TDIR)
t
d(PWM)XCO
PWMx
XCLKOUT
(A)
t
w(PWM)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T APRIL 2001REVISED MAY 2012
www.ti.com
6.17 Event Manager Interface
6.17.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
Table 6-18. PWM Switching Characteristics
(1)(2)
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
w(PWM)
(3)
Pulse duration, PWMx output high/low 25 ns
Delay time, XCLKOUT high to PWMx
t
d(PWM)XCO
XCLKOUT = SYSCLKOUT/4 10 ns
output switching
(1) See the GPIO output timing for fall/rise times for PWM pins.
(2) PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
(3) PWM outputs may be 100%, 0%, or increments of t
c(HCO)
with respect to the PWM period.
Table 6-19. Timer and Capture Unit Timing Requirements
(1)(2)
MIN MAX UNIT
Without input qualifier 2t
c(SCO)
t
w(TDIR)
Pulse duration, TDIRx low/high cycles
With input qualifier 1t
c(SCO)
+ IQT
(3)
Without input qualifier 2t
c(SCO)
t
w(CAP)
Pulse duration, CAPx input low/high cycles
With input qualifier 1t
c(SCO)
+ IQT
(3)
t
w(TCLKINL)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time 40 60 %
t
w(TCLKINH)
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time 40 60 %
t
c(TCLKIN)
Cycle time, TCLKINx 4t
c(HCO)
ns
(1) The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling
period is 2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the
qualification sampling period is 1 × 2 = 2 SYSCLKOUT cycles (that is, the input is sampled every 2 SYSCLKOUT cycles). Six such
samples will be taken over five sampling windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width
that is needed is 5 × 2 = 10 SYSCLKOUT cycles. However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide
pulse ensures reliable recognition.
(2) Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
(3) Input Qualification Time (IQT) = [t
c(SCO)
× 2 × QUALPRD] × 5 + [t
c(SCO)
× 2 × QUALPRD].
A. XCLKOUT = SYSCLKOUT
Figure 6-18. PWM Output Timing
A. XCLKOUT = SYSCLKOUT
Figure 6-19. TDIRx Timing
112 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

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Texas Instruments TMS320C2810 Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320C2810
CategorySignal Processors
LanguageEnglish

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