TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
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SPRS174T –APRIL 2001–REVISED MAY 2012
Table 6-51. McBSP Switching Characteristics
(1)(2)
NO. PARAMETER MIN MAX UNIT
M1 t
c(CKRX)
Cycle time, CLKR/X CLKR/X int 2P ns
M2 t
w(CKRXH)
Pulse duration, CLKR/X high CLKR/X int D – 5
(3)
D + 5
(3)
ns
M3 t
w(CKRXL)
Pulse duration, CLKR/X low CLKR/X int C – 5
(3)
C + 5
(3)
ns
CLKR int 0 4
M4 t
d(CKRH-FRV)
Delay time, CLKR high to internal FSR valid ns
CLKR ext 3 27
CLKX int 0 4
M5 t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid ns
CLKX ext 3 27
CLKX int 8
Disable time, CLKX high to DX high impedance following last
M6 t
dis(CKXH-DXHZ)
ns
data bit
CLKX ext 14
CLKX int 9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX ext 28
CLKX int 8
M7 t
d(CKXH-DXV)
DXENA = 0 ns
Delay time, CLKX high to DX valid.
CLKX ext 14
Only applies to first bit transmitted when in Data
CLKX int P + 8
Delay 1 or 2 (XDATDLY = 01b or 10b) modes.
DXENA = 1
CLKX ext P + 14
CLKX int 0
DXENA = 0
Enable time, CLKX high to DX driven.
CLKX ext 6
M8 t
en(CKXH-DX)
ns
Only applies to first bit transmitted when in Data
CLKX int P
Delay 1 or 2 (XDATDLY = 01b or 10b) modes.
DXENA = 1
CLKX ext P + 6
FSX int 8
DXENA = 0
Delay time, FSX high to DX valid.
FSX ext 14
M9 t
d(FXH-DXV)
ns
Only applies to first bit transmitted when in Data
FSX int P + 8
Delay 0 (XDATDLY = 00b) mode.
DXENA = 1
FSX ext P + 14
FSX int 0
DXENA = 0
Enable time, FSX high to DX driven.
FSX ext 6
M10 t
en(FXH-DX)
ns
Only applies to first bit transmitted when in Data
FSX int P
Delay 0 (XDATDLY = 00b) mode.
DXENA = 1
FSX ext P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 151
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