INT12
MUX
INT11
INT2
INT1
CPU
(Enable)(Flag)
INTx
INTx.8
PIEIERx[8:1] PIEIFRx[8:1]
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals
or
External
Interrupts
(Enable) (Flag)
IER[12:1]IFR[12:1]
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T –APRIL 2001–REVISED MAY 2012
Figure 3-7. Multiplexing of Interrupts Using the PIE Block
Table 3-12. PIE Peripheral Interrupts
(1)
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
WAKEINT TINT0 ADCINT PDPINTB PDPINTA
INT1 XINT2 XINT1 Reserved
(LPM/WD) (TIMER 0) (ADC) (EV-B) (EV-A)
T1OFINT T1UFINT T1CINT T1PINT CMP3INT CMP2INT CMP1INT
INT2 Reserved
(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)
CAPINT3 CAPINT2 CAPINT1 T2OFINT T2UFINT T2CINT T2PINT
INT3 Reserved
(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)
T3OFINT T3UFINT T3CINT T3PINT CMP6INT CMP5INT CMP4INT
INT4 Reserved
(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)
CAPINT6 CAPINT5 CAPINT4 T4OFINT T4UFINT T4CINT T4PINT
INT5 Reserved
(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)
MXINT MRINT SPITXINTA SPIRXINTA
INT6 Reserved Reserved Reserved Reserved
(McBSP) (McBSP) (SPI) (SPI)
INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
INT9 Reserved Reserved
(CAN) (CAN) (SCI-B) (SCI-B) (SCI-A) (SCI-A)
INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
(1) Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
• No peripheral within the group is asserting interrupts.
• No peripheral interrupts are assigned to the group (example PIE group 12).
Copyright © 2001–2012, Texas Instruments Incorporated Functional Overview 45
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