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TMS320C2810
Texas Instruments TMS320C2810 User Manual
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165
167
Table of Contents
Default Chapter
2
Table of Contents
2
List of Tables
9
1 Tms320F281X, Tms320C281X Dsps
10
Features
10
Getting Started
11
2 Introduction
12
Description
12
Device Summary
13
Hardware Features
13
Pin Assignments
14
Terminal Assignments for the GHH/ZHH Packages
14
TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH Microstar BGA™ (Bottom View)
14
Pin Assignments for the PGF Package
15
TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)
15
Pin Assignments for the PBK Package
16
TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP (Top View)
16
Signal Descriptions
17
3 Functional Overview
26
Memory Map
27
Functional Block Diagram
27
F2812/C2812 Memory Map
28
F2811/C2811 Memory Map
29
F2810/C2810 Memory Map
29
Addresses of Flash Sectors in F2812 and F2811
30
Addresses of Flash Sectors in F2810
30
Wait States
31
Brief Descriptions
32
C28X CPU
32
Memory Bus (Harvard Bus Architecture)
32
Peripheral Bus
32
Real-Time JTAG and Analysis
33
External Interface (XINTF) (2812 Only)
33
Flash (F281X Only)
33
ROM (C281X Only)
33
M0, M1 Sarams
34
L0, L1, H0 Sarams
34
Boot ROM
34
Security
34
Boot Mode Selection
34
Impact of Using the Code Security Module
35
Peripheral Interrupt Expansion (PIE) Block
36
External Interrupts (XINT1, XINT2, XINT13, XNMI)
36
Oscillator and PLL
36
Watchdog
36
Peripheral Clocking
36
Low-Power Modes
36
Peripheral Frames 0, 1, 2 (Pfn)
37
General-Purpose Input/Output (GPIO) Multiplexer
37
32-Bit CPU-Timers (0, 1, 2)
37
Control Peripherals
37
Serial Port Peripherals
38
Register Map
39
Peripheral Frame 0 Registers
39
Peripheral Frame 1 Registers
39
Peripheral Frame 2 Registers
40
Device Emulation Registers
41
External Interface, XINTF (2812 Only)
42
External Interface Block Diagram
42
Timing Registers
43
XREVISION Register
43
XINTF Configuration and Control Register Mappings
43
XREVISION Register Bit Definitions
43
Interrupts
44
Interrupt Sources
44
Multiplexing of Interrupts Using the PIE Block
45
PIE Peripheral Interrupts
45
PIE Configuration and Control Registers
46
External Interrupts
47
External Interrupts Registers
47
System Control
48
Clock and Reset Domains
48
PLL, Clocking, Watchdog, and Low-Power Mode Registers
49
OSC and PLL Block
50
Loss of Input Clock
51
PLLCR Register Bit Definitions
51
PLL-Based Clock Module
52
External Reference Oscillator Clock Option
52
Recommended Crystal/Clock Connection
52
Possible PLL Configuration Modes
52
Watchdog Block
53
Watchdog Module
53
Low-Power Modes Block
54
F281X and C281X Low-Power Modes
54
4 Peripherals
55
32-Bit CPU-Timers
55
CPU-Timers
55
CPU-Timer Interrupts Signals and Output Signal
56
CPU-Timers 0, 1, 2 Configuration and Control Registers
57
Event Manager Modules (EVA, EVB)
58
Module and Signal Names for EVA and EVB
58
EVA Registers
59
General-Purpose (GP) Timers
61
Full-Compare Units
61
Programmable Deadband Generator
61
PWM Waveform Generation
61
Double Update PWM Mode
61
Event Manager a Functional Block Diagram
61
PWM Characteristics
62
Capture Unit
62
Quadrature-Encoder Pulse (QEP) Circuit
62
External ADC Start-Of-Conversion
62
Enhanced Analog-To-Digital Converter (ADC) Module
63
Block Diagram of the F281X and C281X ADC Module
64
ADC Pin Connections with Internal Reference
65
ADC Pin Connections with External Reference
66
ADC Registers
67
Enhanced Controller Area Network (Ecan) Module
68
Ecan Block Diagram and Interface Circuit
69
V Ecan Transceivers for the Tms320F281X and Tms320C281X Dsps
70
Ecan Memory Map
71
CAN Registers
72
Multichannel Buffered Serial Port (Mcbsp) Module
73
Mcbsp Module with FIFO
74
Mcbsp Registers
75
Serial Communications Interface (SCI) Module
77
SCI-A Registers
78
SCI-B Registers
78
Serial Communications Interface (SCI) Module Block Diagram
79
Serial Peripheral Interface (SPI) Module
80
SPI Registers
81
Serial Peripheral Interface Module Block Diagram (Slave Mode)
82
Gpio Mux
83
GPIO Mux Registers
83
GPIO Data Registers
84
Gpio/Peripheral Pin Multiplexing
85
5 Development Support
86
Device and Development Support Tool Nomenclature
86
Documentation Support
87
Tms320X281X Device Nomenclature
87
Tms320X281X Peripheral Selection Guide
87
Community Resources
89
6 Electrical Specifications
91
Absolute Maximum Ratings
91
Recommended Operating Conditions
91
Electrical Characteristics over Recommended Operating Conditions (Unless Otherwise Noted)
92
Current Consumption
93
Tms320F281X Current Consumption by Power-Supply Pins over Recommended Operating Conditions During Low-Power Modes at 150-Mhz SYSCLKOUT
93
Tms320C281X Current Consumption by Power-Supply Pins over Recommended Operating Conditions During Low-Power Modes at 150-Mhz SYSCLKOUT
94
Current Consumption Graphs
95
F2812/F2811/F2810 Typical Current Consumption over Frequency
95
F2812/F2811/F2810 Typical Power Consumption over Frequency
96
C2812/C2811/C2810 Typical Current Consumption over Frequency
96
Reducing Current Consumption
97
Emulator Connection Without Signal Buffering for the DSP
97
C2812/C2811/C2810 Typical Power Consumption over Frequency
97
Typical Current Consumption by Various Peripherals (at 150 Mhz)
97
Power Sequencing Requirements
98
Recommended "Low-Dropout Regulators
98
F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence - Option 2
99
Signal Transition Levels
100
Output Levels
100
Input Levels
100
Timing Parameter Symbology
101
General Notes on Timing Parameters
101
Test Load Circuit
101
V Test Load Circuit
101
Device Clock Table
102
Tms320F281X and Tms320C281X Clock Table and Nomenclature
102
Clock Requirements and Characteristics
103
Input Clock Requirements
103
Input Clock Frequency
103
XCLKIN Timing Requirements - PLL Bypassed or Enabled
103
XCLKIN Timing Requirements - PLL Disabled
103
Possible PLL Configuration Modes
103
Output Clock Characteristics
104
Reset Timing
104
Clock Timing
104
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
104
Reset (XRS) Timing Requirements
104
Power-On Reset in Microcomputer Mode (XMP/MC = 0) (See Note D)
106
Power-On Reset in Microprocessor Mode (XMP/MC = 1)
107
Warm Reset in Microcomputer Mode
107
Effect of Writing into PLLCR Register
107
Low-Power Mode Wakeup Timing
108
IDLE Entry and Exit Timing
108
IDLE Mode Timing Requirements
108
IDLE Mode Switching Characteristics
108
STANDBY Mode Timing Requirements
109
STANDBY Mode Switching Characteristics
109
STANDBY Entry and Exit Timing
110
HALT Wakeup Using XNMI
111
HALT Mode Timing Requirements
111
HALT Mode Switching Characteristics
111
Event Manager Interface
112
PWM Timing
112
PWM Output Timing
112
PWM Switching Characteristics
112
Timer and Capture Unit Timing Requirements
112
Tdirx Timing
113
EVASOC Timing
113
EVBSOC Timing
113
External ADC Start-Of-Conversion - EVA - Switching Characteristics
113
External ADC Start-Of-Conversion - EVB - Switching Characteristics
113
Interrupt Timing
114
External Interrupt Timing
114
Interrupt Switching Characteristics
114
Interrupt Timing Requirements
114
General-Purpose Input/Output (GPIO) - Output Timing
115
General-Purpose Output Timing
115
General-Purpose Output Switching Characteristics
115
General-Purpose Input/Output (GPIO) - Input Timing
116
GPIO Input Qualifier - Example Diagram for QUALPRD = 1
116
Serial Peripheral Interface (SPI) Master Mode Timing
117
General-Purpose Input Timing
117
General-Purpose Input Timing Requirements
117
SPI Master Mode External Timing (Clock Phase = 0)
118
SPI Master Mode External Timing (Clock Phase = 0)
119
SPI Master Mode External Timing (Clock Phase = 1)
120
SPI Master External Timing (Clock Phase = 1)
121
Serial Peripheral Interface (SPI) Slave Mode Timing
122
SPI Slave Mode External Timing (Clock Phase = 0)
122
SPI Slave Mode External Timing (Clock Phase = 0)
123
SPI Slave Mode External Timing (Clock Phase = 1)
124
SPI Slave Mode External Timing (Clock Phase = 1)
125
External Interface (XINTF) Timing
126
Relationship between Parameters Configured in XTIMING and Duration of Pulse
126
Relationship between XTIMCLK and SYSCLKOUT
129
XINTF Clock Configurations
129
XINTF Signal Alignment to XCLKOUT
130
External Interface Read Timing
131
External Memory Interface Read Switching Characteristics
131
External Memory Interface Read Timing Requirements
131
Example Read Access
132
External Interface Write Timing
133
Example Write Access
133
External Memory Interface Write Switching Characteristics
133
External Interface Ready-On-Read Timing with One External Wait State
134
External Memory Interface Read Switching Characteristics (Ready-On-Read, 1 Wait State)
134
External Memory Interface Read Timing Requirements (Ready-On-Read, 1 Wait State)
134
Synchronous XREADY Timing Requirements (Ready-On-Read, 1 Wait State)
134
Asynchronous XREADY Timing Requirements (Ready-On-Read, 1 Wait State)
134
Example Read with Synchronous XREADY Access
135
Example Read with Asynchronous XREADY Access
136
External Interface Ready-On-Write Timing with One External Wait State
137
External Memory Interface Write Switching Characteristics (Ready-On-Write, 1 Wait State)
137
Synchronous XREADY Timing Requirements (Ready-On-Write, 1 Wait State)
137
Asynchronous XREADY Timing Requirements (Ready-On-Write, 1 Wait State)
137
Write with Synchronous XREADY Access
138
Write with Asynchronous XREADY Access
139
XHOLD and XHOLDA
140
XHOLD/XHOLDA Timing
141
External Interface Hold Waveform
141
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
141
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
142
On-Chip Analog-To-Digital Converter
143
ADC Absolute Maximum Ratings
143
ADC Electrical Characteristics over Recommended Operating Conditions
144
DC Specifications
144
Current Consumption for Different ADC Configurations
145
AC Specifications
145
Current Consumption for Different ADC Configurations (at 25-Mhz ADCCLK)
145
ADC Power-Up Control Bit Timing
146
Detailed Description
146
Reference Voltage
146
Analog Inputs
146
Converter
146
Conversion Modes
146
ADC Analog Input Impedance Model
146
ADC Power-Up Delays
146
Sequential Sampling Mode (Single-Channel) (SMODE = 0)
147
Sequential Sampling Mode (Single-Channel) Timing
147
Sequential Sampling Mode Timing
147
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
148
Simultaneous Sampling Mode Timing
148
Definitions of Specifications and Terminology
149
Multichannel Buffered Serial Port (Mcbsp) Timing
150
Mcbsp Transmit and Receive Timing
150
Mcbsp Timing Requirements
150
Mcbsp Switching Characteristics
151
Mcbsp Receive Timing
152
Mcbsp Transmit Timing
152
Mcbsp as SPI Master or Slave Timing
153
Mcbsp Timing as SPI Master or Slave: CLKSTP = 10B, CLKXP
153
Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 10B, CLKXP = 0)
153
Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 10B, CLKXP = 0)
153
Mcbsp Timing as SPI Master or Slave: CLKSTP = 11B, CLKXP
154
Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 11B, CLKXP = 0)
154
Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 11B, CLKXP = 0)
154
Mcbsp Timing as SPI Master or Slave: CLKSTP = 10B, CLKXP = 1
155
Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 10B, CLKXP = 1)
155
Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 10B, CLKXP = 1)
155
Mcbsp Timing as SPI Master or Slave: CLKSTP = 11B, CLKXP = 1
156
Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 11B, CLKXP = 1)
156
Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 11B, CLKXP = 1)
156
Flash Timing (F281X Only)
157
Flash Parameters at 150-Mhz SYSCLKOUT
157
Flash/Otp Access Timing
158
Minimum Required Flash Wait States at Different Frequencies (F281X Devices)
158
ROM Access Timing
159
Minimum Required ROM Wait States at Different Frequencies (C281X Devices)
159
ROM Timing (C281X Only)
159
Migrating from F281X Devices to C281X Devices
160
7 Revision History
161
8 Mechanical Data
162
Thermal Resistance Characteristics for 179-Ball GHH
162
Thermal Resistance Characteristics for 179-Ball ZHH
162
Thermal Resistance Characteristics for 176-Pin PGF
162
Thermal Resistance Characteristics for 128-Pin PBK
162
4
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Texas Instruments TMS320C2810 Specifications
General
Brand
Texas Instruments
Model
TMS320C2810
Category
Signal Processors
Language
English
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