Texas Instruments TMS320C2810 - Page 5

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com SPRS174T –APRIL 2001–REVISED MAY 2012
List of Figures
2-1 TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)............................. 14
2-2 TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View) ..................................................... 15
2-3 TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP (Top View).............. 16
3-1 Functional Block Diagram....................................................................................................... 27
3-2 F2812/C2812 Memory Map..................................................................................................... 28
3-3 F2811/C2811 Memory Map..................................................................................................... 29
3-4 F2810/C2810 Memory Map..................................................................................................... 29
3-5 External Interface Block Diagram .............................................................................................. 42
3-6 Interrupt Sources ................................................................................................................. 44
3-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 45
3-8 Clock and Reset Domains ...................................................................................................... 48
3-9 OSC and PLL Block.............................................................................................................. 50
3-10 Recommended Crystal/Clock Connection .................................................................................... 52
3-11 Watchdog Module ................................................................................................................ 53
4-1 CPU-Timers....................................................................................................................... 55
4-2 CPU-Timer Interrupts Signals and Output Signal............................................................................ 56
4-3 Event Manager A Functional Block Diagram ................................................................................. 61
4-4 Block Diagram of the F281x and C281x ADC Module ...................................................................... 64
4-5 ADC Pin Connections With Internal Reference .............................................................................. 65
4-6 ADC Pin Connections With External Reference ............................................................................. 66
4-7 eCAN Block Diagram and Interface Circuit ................................................................................... 69
4-8 eCAN Memory Map .............................................................................................................. 71
4-9 McBSP Module With FIFO ...................................................................................................... 74
4-10 Serial Communications Interface (SCI) Module Block Diagram............................................................ 79
4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 82
4-12 GPIO/Peripheral Pin Multiplexing .............................................................................................. 85
5-1 TMS320x281x Device Nomenclature.......................................................................................... 87
6-1 F2812/F2811/F2810 Typical Current Consumption Over Frequency ..................................................... 95
6-2 F2812/F2811/F2810 Typical Power Consumption Over Frequency....................................................... 96
6-3 C2812/C2811/C2810 Typical Current Consumption Over Frequency .................................................... 96
6-4 C2812/C2811/C2810 Typical Power Consumption Over Frequency...................................................... 97
6-5 Emulator Connection Without Signal Buffering for the DSP................................................................ 98
6-6 F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2 ....................................... 99
6-7 Output Levels.................................................................................................................... 100
6-8 Input Levels...................................................................................................................... 100
6-9 3.3-V Test Load Circuit......................................................................................................... 101
6-10 Clock Timing..................................................................................................................... 104
6-11 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D) ................................................. 106
6-12 Power-on Reset in Microprocessor Mode (XMP/MC = 1) ................................................................. 107
6-13 Warm Reset in Microcomputer Mode ........................................................................................ 107
6-14 Effect of Writing Into PLLCR Register ....................................................................................... 107
6-15 IDLE Entry and Exit Timing.................................................................................................... 108
6-16 STANDBY Entry and Exit Timing............................................................................................. 110
6-17 HALT Wakeup Using XNMI ................................................................................................... 111
6-18 PWM Output Timing............................................................................................................ 112
6-19 TDIRx Timing.................................................................................................................... 113
6-20 EVASOC Timing ................................................................................................................ 113
Copyright © 2001–2012, Texas Instruments Incorporated List of Figures 5