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TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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Terminal Configuration and Functions Copyright © 2013–2016, Texas Instruments Incorporated
4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-12. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)
Terminal Signal
Type
Reset Pull
State
Pull Type Description
Signal Name 144
PGE
MIBSPI1CLK 95 I/O Pullup Programmable,
20 µA
MibSPI1 clock, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105 MibSPI1 chip select, or
GIO
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S 130
MIBSPI1NCS[2]/N2HET1[19]/ 40
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 Pulldown Programmable,
20 µA
MibSPI1 chip select, or
GIO
N2HET1[24]/MIBSPI1NCS[5] 91
MIBSPI1NENA/N2HET1[23]/ECAP4 96 Pullup Programmable,
20 µA
MibSPI1 enable, or GIO
MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-
out, or GIO
N2HET1[08]/MIBSPI1SIMO[1] 106 Pulldown Programmable,
20 µA
MibSPI1 slave-in master-
out, or GIO
MIBSPI1SOMI[0] 94 Pullup Programmable,
20 µA
MibSPI1 slave-out master-
in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 I/O Pullup Programmable,
20 µA
MibSPI3 clock, or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD
IS
55 MibSPI3 chip select, or
GIO
MIBSPI3NCS[1]/N2HET1[25] 37
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2 4
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1 3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 Pulldown Programmable,
20 µA
MibSPI3 chip select, or
GIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pullup Programmable,
20 µA
MibSPI3 chip select, or
GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 MibSPI3 enable, or GIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 MibSPI3 slave-in master-
out, or GIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 MibSPI3 slave-out master-
in, or GIO
MIBSPI5CLK 100 I/O Pullup Programmable,
20 µA
MibSPI5 clock, or GIO
MIBSPI5NCS[0]/EPWM4A 32 MibSPI5 chip select, or
GIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 97 MibSPI5 enable, or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 slave-in master-
out, or GIO
MIBSPI5SOMI[0] 98 MibSPI5 slave-out master-
in, or GIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 97 MibSPI5 SOMI[0], or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 SOMI[0], or GIO