Copyright © 2013–2016, Texas Instruments IncorporatedTerminal Configuration and Functions
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TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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Table 4-37. Multiplexing for Outputs on 144-Pin PGE Package(1)
144-PIN
PGE
DEFAULT
FUNCTION
CTRL1 OPTION 2 CTRL2 OPTION 3 CTRL3 OPTION 4 CTRL4 OPTION 5 CTRL5 OPTION 6 CTRL6
86 AD1EVT 10[0]
2 GIOA[0] 0[8]
5 GIOA[1] 1[0]
9 GIOA[2] 2[0] N2HET2[0] 2[3] EQEP2I 2[4]
14 GIOA[5] 2[24] EXTCLKIN1 2[25] EPWM1A 2[26]
16 GIOA[6] 3[16] N2HET2[4] 3[17] EPWM1B 3[18]
22 GIOA[7] 4[0] N2HET2[6] 4[1] EPWM2A 4[2]
126 GIOB[0] 18[24]
133 GIOB[1] 21[8]
1 GIOB[3] 0[0]
105 MIBSPI1NCS[0] 13[24] MIBSPI1SOMI[1] 13[25] ECAP6 13[28]
130 MIBSPI1NCS[1] 20[16] N2HET1[17] 20[17] EQEP1S 20[20]
40 MIBSPI1NCS[2] 8[8] N2HET1[19] 8[9]
96 MIBSPI1NENA 12[16] N2HET1[23] 12[17] ECAP4 12[20]
53 MIBSPI3CLK 33[24] AWM1_EXT_SEL[1] 33[25] EQEP1A 33[26]
55 MIBSPI3NCS[0] 9[16] AD2EVT 9[17] GIOB[2] 9[18] EQEP1I 9[19]
37 MIBSPI3NCS[1] 7[8] N2HET1[25] 7[9]
4 MIBSPI3NCS[2] 0[24] I2C_SDA 0[25] N2HET1[27] 0[26] nTZ2 0[27]
3 MIBSPI3NCS[3] 0[16] I2C_SCL 0[17] N2HET1[29] 0[18] nTZ1 0[19]
54 MIBSPI3NENA 9[8] MIBSPI3NCS[5] 9[9] N2HET1[31] 9[10] EQEP1B 9[11]
52 MIBSPI3SIMO 33[16] AWM1_EXT_SEL[0] 33[17] ECAP3 33[18]
51 MIBSPI3SOMI 33[8] AWM1_EXT_ENA 33[9] ECAP2 33[10]
100 MIBSPI5CLK 13[16]
32 MIBSPI5NCS[0] 27[0] EPWM4A 27[2]
97 MIBSPI5NENA 12[24] MIBSPI5SOMI[1] 12[28] ECAP5 12[29]
99 MIBSPI5SIMO[0] 13[8] MIBSPI5SOMI[2] 13[12]
98 MIBSPI5SOMI[0] 13[0]
25 N2HET1[0] 5[0] SPI4CLK 5[1] EPWM2B 5[2]
23 N2HET1[01] 4[16] SPI4NENA 4[17] 4[19] N2HET2[8] 4[20] EQEP2A 4[21]
30 N2HET1[02] 5[8] SPI4SIMO 5[9] EPWM3A 5[10]
24 N2HET1[03] 4[24] SPI4NCS[0] 4[25] 4[27] N2HET2[10] 4[28] EQEP2B 4[29]
36 N2HET1[04] 33[0] EPWM4B 33[1]
31 N2HET1[05] 5[16] SPI4SOMI 5[17] N2HET2[12] 5[18] EPWM3B 5[19]
38 N2HET1[06] 7[16] SCIRX 7[17] EPWM5A 7[18]
33 N2HET1[07] 6[0] N2HET2[14] 6[3] EPWM7B 6[4]
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