65
TMS570LS0714
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SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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System Information and Electrical SpecificationsCopyright © 2013–2016, Texas Instruments Incorporated
6.9.4 Master/Slave Access Privileges
Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that
can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. Yes indicates that the module listed in
the MASTERS column can access that slave module.
Table 6-21. Master / Slave Access Matrix
MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module
Bus2 Interface:
OTP, ECC, Bank
7
Non-CPU
Accesses to
Program Flash
and CPU Data
RAM
CRC Slave Interfaces Peripheral
Control
Registers, All
Peripheral
Memories, And
All System
Module Control
Registers And
Memories
CPU READ User/Privilege Yes Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes Yes
DMA User Yes Yes Yes Yes Yes
DAP Privilege Yes Yes Yes Yes Yes
HTU1 Privilege No Yes Yes Yes Yes
HTU2 Privilege No Yes Yes Yes Yes
6.9.5 Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned off.
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