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TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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System Information and Electrical Specifications Copyright © 2013–2016, Texas Instruments Incorporated
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
6.10.5 Program Flash
Table 6-23. Timing Requirements for Program Flash
MIN NOM MAX UNIT
t
prog(144bit)
Wide Word (144-bit) programming time 40 300 µs
t
prog(Total)
768KB programming time
(1)
–40°C to 125°C 8 s
0°C to 60°C, for first
25 cycles
2 4 s
t
erase(bank0)
Sector/Bank erase time
(2)
–40°C to 125°C 0.03 4 s
0°C to 60°C, for first
25 cycles
16 100 ms
t
wec
Write/erase cycles with 15-year Data Retention
requirement
–40°C to 125°C 1000 cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 72 bits at a time at the maximum specified operating frequency.
6.10.6 Data Flash
Table 6-24. Timing Requirements for Data Flash
MIN NOM MAX UNIT
t
prog(144bit)
Wide Word (72-bit) programming time 47 310 µs
t
prog(Total)
EEPROM Emulation (bank 7) 64KByte
programming time
(1)
–40°C to 125°C 2.6 s
0°C to 60°C, for first
25 cycles
775 1435 ms
t
erase(bank7)
Sector/Bank erase time, EEPROM Emulation
(bank 7)
–40°C to 125°C 0.2 8 s
0°C to 60°C, for first
25 cycles
14 100 ms
t
wec
Write/erase cycles with 15-year Data Retention
requirement
–40°C to 125°C 100000 cycles
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