the next break point is
encountered.Theflipflopsof
U23
pressed, the microprocessor pulls
MANHOLD (U27B pin
are reset after each trigger. When the manual trigger 4) low which also turns off the "run" signal.
key
pressed'
the
microprocessor
'Oggles
TheSync In and Return In inputsare also routed through
(U15B pin 5). That creates the same sequence of events
the trigger and hold logic. A low applied to the Return
as
an
external trigger'
5B
pin
5,
is
also
used
In
connector appears at U12E pin 1 1 (RETURN IN), The
tocontrol the trigger slope of the external trigger signal.
output of U 1 2E (pin 1 0) is sent to the microprocessor sec-
When
positive
t
rigger
is
selected.
is
tion where it is t
rested
the
same
as
a
key
press,
The Sync
high
When
negative trigger 'lope
is
selected!
In input is connected directly to U21A pin 1, The
is set low. While the trigger slope is being changed. the
of
U21A (SYNC IN)
is
sent
to
the
waveform
address
sets
TRIGMASK (U23B pin
2,
low
counter where it will restart the
waveform
when
prevent
the
change in
causing
a
asserted, The signal SYNCEN originates in the waveform
trigger.
latch (ref: schematic 0103-00-1 456 sheet 3). It's func-
The operation of gated mode is similar to triggered
tion is to block any sync input while the microprocessor
except an additional requirement must be met before
is setting up a return to start. It is pulled low
during this
a break point will stop the waveform clock. The GATE
time.
bit (U21
B pin 4) is set high by the microprocessor. As
long as the trigger input is asserted, U21
B pin 5 is held
4.2.2.4 Burst Counter
high and TPOINT is not gated through U22C. Once the
trigger input is released, U21 B pin
5goes low and allows
the next TPOINT through
U22C to stop the waveform
clock.
When toggle mode is selected, the microprocessor sets
TGL
(U15C pin 9) and GATE (U21 B pin 4) high. This
disables the trigger path through
U26D and enables the
flip flop
U24B, which is configured as adivide by 2. Every
rising edge on the clock input of
U24B (pin 11) causes
U21
B pin 5 to change states. This means toggled opera-
tion is the same as gated except the control line at U21 B
pin 5 is set high by a trigger pulse and held until the next
trigger pulse.
Burst mode is similar to gated and toggled in that more
than one condition must be met to stop the waveform
clock and thereby the waveform. When burst mode is
selected, the microprocessor sets
BURST(U21 D pin 12)
high and sends the selected burst count to the burst
counter (ref: schematic 01 03-00-1 389 sheet 4). When
a trigger pulse clocks
U230, itlsa(pin 8)goes low to start
the waveform clock. The
Q
output of U23B (pin 9) goes
high and loads the burst count into the burst counters.
The output of the burst counter is STOPOK
(U2'1 D pin
13). This line is held high until the selected burst count
is reached. While it is high TPOINT is stopped at
U22C.
When the burst count is reached, STOPOK is pulled low
and the next TPOINT is allowed through
U22C to stop
the waveform clock. The Burst Done Output
(U25B pin
4) is simply an inverted version of the TPOINT signal and
tells the outside world that the waveform is stopped.
The Hold In input works in much the same way as the
trigger control circuitry in that it controls the ''run'' signal
to the whole pulse circuit and thus the waveform clock.
When a low is applied to the Hold In connector it appears
at U21 F pin 13 (HOLD IN). This pulls
U27C pin 10 low
and turns off the "run" signal. When the hold key is
Refer to schematic 01 03-00-1 389, sheet 4. The burst
counter contains five programmable 4 bit binary
counters(U50, U51, U43, U41, and U40)and threeoctal
D type flip flops
(U47, U42, and U44). The counters are
cascaded to form a 20 bit binary counter with
U50 pin
14 the least significant bit and
U40pin 11 the most signifi-
cant. The microprocessor converts the decimal burst
count set by the user to a binary number and writes the
1's compliment of that number to the preload inputs of
the counters (pins
3,4,5 and 6 of U50, U51, U43, U41
and
U40). For instance; if the burst count is set to the
largest possible setting, 1,048,575, the preload inputs
to the counters are set to all zeros. When the instrument
is triggered,
BURLOAD (U50 pin 9) is pulled low by the
trigger and hold logic and loads the binary burst count
into the counters. The counters are clocked by the
waveform clock
(U50 pin 2) but only count when BCEN
(U50 pin 7) is high. BCEN is generated at the waveform
address counter from the bit in the waveform memory
that sets the waveform stop address; LOAD (ref:
schematic 01 03-00-1 389 sheet 3). Since BCEN is high
for only one clock pulse, the burst counter, starting at
the preset number, increments one for every waveform
that is output. When the burst counter reaches it's full
value (all ones) the carry out on U40 pin 15 (STOPOK)
is sent to the trigger logic to stop the waveform clock.
It is also gated with the load pulse (ref: schematic
01 03-00-1 389 sheet 3;
U15C) to force BCEN low and pre-
vent further counting. This is done to prevent burst
counter overflow if the microprocessor isaccessing the
waveform memory when a break point occurs.
Theoctal flip flops(U47, U42and U44)act asdata latches
between the burst counter and the microprocessor data
bus. This allows the microprocessor to read the current
value of the burst counter and
fac~litates the internal
waveform counter. When the instrument is in gated or
Scans
by
ArtekMedia
O
2006
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