accessed. When this occurs the GPIA sets its address
switch enable line (U2 pin 4)
low.This causes the buffer,
U1, to transfer theaddress, asset bySW1, to themicro-
processor data bus. The microprocessor then writes this
address into an address register in the GPIA. For more
information on the
GPlBaddress, refer to Section 2.2.6.
4.2.4.3 RS-232-C (Option 002)
Refer to schematic 01 03-00-1 677. The RS-232-Coption
consists of an asynchronous communication interface
adapter
(Ul), a baud rate generator (~2)~' a quad line
driver
(U3), a quad line receiver (U4) and a 5 position
SPST switch
(SW1). The asynchronous communication
interface adapter (ACIA) interfaces between the parallel
communication of the microprocessor section and the
asynchronous serial communication of the RS-232
interface. All RS-232 transactions are handled by the
AClA which alerts the microprocessor when it needs
attention.
Data and control lines that are output to the interface
are driven by U3. This line driver inverts and translates
the
lTL
logic levels from the AClA to
f
12V (nominal)
logic that meets the RS-232 specifications. The
capacitors, C7 and
C9, reduce the slew rate of the out-
puts to meet RS-232 specifications. Data and control
lines that are input from the bus are received by
U4.This
line receiver translates and inverts the widely varying
logic levels from the bus, into
lTL
logic levels for the
ACIA. Any input between
+
3V and
+
25V is detected
as a logic
"0" and between
-
3V and
-
25V is a logic
"1 ".The
capacitorsC8, C10 andC11 act as noise filters
for the inputs. For a detailed description of the RS-232
signals refer to Sections 2.2.7 and 3.31.
The baud rate of the transmitted data is determined by
the frequency input to pins 3 and 4 of Ul, which is 16
times the baud rate. The source of this frequency is the
baud rate generator U2. U2 has an internal oscillator
whose frequency is based on the 2.4576 Mhz crystal,
Y1. Using internal dividers, the output frequency of U2
can be set to one of 14 frequencies with
SW1 switches
1 thru 4. Table 2-4 shows the baud rate switch settings.
The
AClA contains internal registers for transmit data,
receive data, status and control. Of these registers,
transmit data and control are write only and the others
are read only. These registers are accessed by the
microprocessor via the data bus AD7-ADO
(U1 pins
15-22). The microprocessor section enables the
AClA
by setting
COMM
(U1 pin 9) low. The least significant
address line (ADRO) drives the register select pin of
U1
(pin 11). This lineselects either the transmittreceivedata
registers when high or the controllstatus registers when
low. The microprocessor readlwrite control
(U1 pin 13)
is used in conjunction with the register select to select
the
readonlyorwriteonly register of each pair. The
"E"
clock (U 1 pin 1 4) from the microprocessor synchronizes
the data transfer. When the AClA needs attention from
the microprocessor it pulls
IRQ
(U1 pin 7) low. The
microprocessor then executes an interrupt service
routine which reads the status register and performs the
necessary data transfer.
4.2.5 Power Supply
4.2.5.1 General Description
Three DC power supply voltages are generated on the
power supply circuit board;
+
15V and
+
5V. These
voltages are generated from either 11
SVac or 230Vac
line as selected by the user. See section 2.2.3 for line
voltage information.
4.2.5.2
+
5V Power Supply
Refer to schematic 01 03-00-1 11 3. AC voltage from the
transformer,
TI, is rectified by thediode bridgeCR2 and
filtered by
thecapacitorsC1 OandC11. This providesan
unregulated
DCvoltagefor the
+
5V regulator VR2. The
capacitor, C12 provides filtering of high frequency noise
and insures the stability of VR2. The capacitor,
C9 pro-
tects against high voltage transients on the AC line that
couple onto the transformer secondary.
4.2.5.3
5
15V Power Supply
Refer to schematic 01 03-00-1 11 3. The transformer, T1
provides an ACvoltagewith a ground referenced center
tap. This voltage is rectified by
thediode bridgeCR1 and
filtered by the capacitors C2, C3, C4 and
C5. 'This pro-
vides unregulated
+
DC voltages for the regulator VR1.
The capacitor, C1 protects against high voltage tran-
sients on the AC line that couple onto the transformer
secondary. For the
+
1 5V supply, VR1 senses the out-
put voltage at pin
14and modulates the baseof the pass
device,
Q1, thus regulating the output voltage. The
capacitors, C6 and C8, provide filtering at the regulator
output. The load current causes a voltage drop across
the resistor, R2. When the loadcurrent reaches its limit,
the regulator senses the drop across R2 and reduces
theoutput voltage until the current falls below the limiting
value. The
-
15V supply operates in a similar manner
and tracks the
+
15V supply.
Scans
by
ArtekMedia
O
2006
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