Xilinx Spartan-3E - Page 149

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Spartan-3E Start Kit Board User Guide www.xilinx.com 149

UG230 (v1.0) March 9, 2006

XC2C64A CoolRunner-II CPLD

R

Figure A-9:

Schematic Sheet 10

UG230_Aa_09_021806

Table of Contents

Default Chapter2
- Revision History2
- Table of Contents3
- FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG7
- FPGA I/O Banks 2 and 3" • "Power Supply Decoupling7
- RS-232 Ports, VGA Port, and PS/2 Port7
- This Appendix Provides the Following Circuit Board Schematics:7
Preface: about this Guide9
- Acknowledgements9
- Guide Contents9
- Additional Resources10
  - XC2C64A Coolrunner-II CPLD10
Chapter 1: Introduction and Overview11
- Choose the Starter Kit Board for Your Needs11
- Key Components and Features12
- Design Trade-Offs13
  - Configuration Methods Galore13
  - Voltages for All Applications13
- Related Resources13
Chapter 2: Switches, Buttons, and Knob15
- Slide Switches15
- Push-Button Switches16
- Rotary Push-Button Switch17
- Discrete Leds19
- Related Resources20
Chapter 3: Clock Sources21
- Overview21
- Auxiliary Clock Oscillator Socket22
- SMA Clock Input or Output Connector22
- UCF Constraints22
  - Location22
  - Clock Period Constraints23
- Clock Connections22
- Voltage Control22
- 50 Mhz On-Board Oscillator22
- Related Resources23
Chapter 4: FPGA Configuration Options25
- Configuration Mode Jumpers26
- PROG Push Button27
- DONE Pin LED27
- Programming the FPGA, CPLD, or Platform Flash PROM Via USB28
Chapter 5: Character LCD Screen41
- Overview41
- Character LCD Interface Signals42
- Voltage Compatibility42
- Interaction with Intel Strataflash42
- UCF Location Constraints43
- LCD Controller43
  - Memory Map43
  - Command Set46
- Operation50
- Related Resources52
Chapter 6: VGA Display Port53
- Signal Timing for a 60 Hz, 640X480 VGA Display54
- VGA Signal Timing56
- UCF Location Constraints57
- Related Resources57
Chapter 7 : RS-232 Serial Ports59
- Overview59
- UCF Location Constraints60
Chapter 8: PS/2 Mouse/Keyboard Port61
- Keyboard62
- Mouse64
- Voltage Supply65
- UCF Location Constraints65
- Related Resources65
Chapter 9: Digital to Analog Converter (DAC)67
- SPI Communication67
- Specifying the DAC Output Voltage70
  - DAC Outputs a and B70
  - DAC Outputs C and D70
- UCF Location Constraints71
- Related Resources71
Chapter 10: Analog Capture Circuit73
- Digital Outputs from Analog Inputs74
- Programmable Pre-Amplifier75
- Analog to Digital Converter (ADC)77
- Connecting Analog Inputs79
- Related Resources79
- Disable Other Devices on the SPI Bus to Avoid Contention79
Chapter 11: Intel Strataflash Parallel nor Flash PROM81
- Strataflash Connections82
- Shared Connections85
- UCF Location Constraints86
- Setting the FPGA Mode Select Pins87
- Related Resources87
Chapter 12: SPI Serial Flash89
- UCF Location Constraints89
- Configuring from SPI Flash90
- Additional Design Details99
- Related Resources102
Chapter 13: DDR SDRAM103
- DDR SDRAM Connections104
- UCF Location Constraints106
- Related Resources107
Chapter 14: 10/100 Ethernet Physical Layer Interface110
- Ethernet PHY Connections110
- Microblaze Ethernet IP Cores111
- UCF Location Constraints112
- Related Resources112
Chapter 15: Expansion Connectors113
- Hirose 100-Pin FX2 Edge Connector (J3)113
- Six-Pin Accessory Headers121
- UCF Location Constraints122
- Connectorless Debugging Port Landing Pads (J6)123
- Related Resources124
Chapter 16: XC2C64A Coolrunner-II CPLD125
- UCF Location Constraints127
  - FPGA Connections to CPLD127
  - Cpld127
- Related Resources128
Chapter 17: DS2432 1-Wire SHA-1 EEPROM129
- UCF Location Constraints129
- Related Resources129
Appendix A: Schematics132
- FX2 Expansion Header, 6-Pin Headers, and Connectorless Probe Header132
- RS-232 Ports, VGA Port, and PS/2 Port134
- Ethernet PHY, Magnetics, and RJ-11 Connector136
- Voltage Regulators138
- FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections140
- FPGA I/O Banks 0 and 1, Oscillators142
- FPGA I/O Banks 2 and 3144
- Power Supply Decoupling146
- XC2C64A Coolrunner-II CPLD148

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