Xilinx Spartan-6 FPGA Series User Manual

72 pages

To Next Page

To Previous Page

62 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning

UG393 (v1.1) April 29, 2010

Chapter 6: I/O Pin and Clock Planning

that require V

REF

pins in bank 1 and also use the BPI configuration mode. Designers need

to review the tradeoffs before dedicating multi-function pins.

Designs using the Master SelectMAP configuration mode must be able to manage toggling

pins during configuration since the address bus A[25:0], and the BUSY, FOE_B, FCS_B, and

FWE_B multi-function pins can toggle during the configuration process.

Memory Controller Block

The BPI configuration mode cannot be used when the design uses the memory controller

block (MCB) in bank 1. Conversely, when configuring in BPI mode, the MCB in bank 1 can

not be used.

Configuration Options

Proper design planning considers any pins required by the configuration options.

Readback

Ensure that the configuration pins that will persist as configuration pins for readback are

not used as user I/O by the design. The table in the Reserving Dual-Purpose Configuration

Pins (Persist) section (Chapter 5) of the Spartan-6 FPGA Configuration Guide lists the pins

that will persist for each configuration mode.

Readback CRC

Readback CRC requires that the INIT_B pin be used as the CRC error flag. Therefore, the

INIT_B pin is not available as a user I/O unless the CRC error flag is disabled by using the

constraint: POST_CRC_INIT_FLAG = DISABLE. Chapter 8 of the Spartan-6 FPGA

Configuration Guide contains more details on Readback CRC including a UCF file design

implementation example.

External Clock Option for Master Configuration Modes

The USERCCLK option for the Master configuration modes uses the same I/O as the

GCLK0 pin.

Memory Controller Block

MCB Pin Planning Considerations

The Spartan-6 FPGA MCB shares multi-function I/O pins with other functions such as

GCLK and configuration pins. When using these pins for the MCB, they cannot be used for

the other functions. The Memory Interface Generator (MIG) tool in the Core Generator

software generates the specific pin assignments for each MCB.

Note:

The MCB in I/O bank 1 has the most multi-function pin conflicts. To avoid these conflicts, use

the MCBs in other I/O banks whenever possible.

In addition to the typical interface pins associated with memory interfaces, two additional

user I/O pins are usually required: RZQ and ZIO. The MIG tool adds these two additional

I/O pins automatically. See the Spartan-6 FPGA Memory Controller User Guide for more

information on their usage and required terminations.

Need help?

Do you have a question about the Xilinx Spartan-6 FPGA Series and is the answer not in the manual?

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156