Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 31
UG393 (v1.1) April 29, 2010
Basic PDS Principles
A finite time delay (Equation 2-6) occurs between the start of the disturbance at the FPGA
power pins and the point when the capacitor senses the disturbance.
Equation 2-6
The dielectric is the substrate of the PCB where the power planes are embedded.
Another delay of the same duration occurs when the compensation current from the
capacitor flows to the FPGA. For any transient current demand in the FPGA, a round-trip
delay occurs before any relief is seen at the FPGA.
• Negligible energy is transferred to the FPGA with placement distances greater than
one quarter of a demand frequency’s wavelength.
• Energy transferred to the FPGA increases from 0% at one-quarter of a wavelength to
100% at zero distance.
• Energy is transferred efficiently from the capacitor to the FPGA when capacitor
placement is at a fraction of a quarter wavelength of the FPGA power pins. This
fraction should be small because the capacitor is also effective at some frequencies
(shorter wavelengths) above its resonant frequency.
One-tenth of a quarter wavelength is a good target for most practical applications and
leads to placing a capacitor within one-fortieth of a wavelength of the power pins it is
decoupling. The wavelength corresponds to the capacitor's mounted resonant frequency,
F
RIS
.
When using large numbers of external termination resistors or passive power filtering for
transceivers, priority should be given to these over the decoupling capacitors. Moving
away from the device in concentric rings, the termination resistors and transceiver supply
filtering should be closest to the device, followed by the smallest-value decoupling
capacitors, then the larger-value decoupling capacitors.
V
REF
Stabilization Capacitors
In V
REF
supply stabilization, one capacitor per pin is placed as close as possible to the V
REF
pin. The capacitors used are in the 0.022 µF - 0.47 µF range. The V
REF
capacitor’s primary
function is to reduce the V
REF
node impedance, which in turn reduces crosstalk coupling.
Since no low-frequency energy is needed, larger capacitors are not necessary.
Power Supply Consolidation
To design for reduced noise-levels on the V
CCAUX
supply, separate supplies should be
provided for V
CCAUX
and any of the V
CCO
voltage rails. However, a common supply to
both V
CCAUX
and V
CCO
pins (at either 2.5V or 3.3V) is allowed as long as the
recommended operating conditions for the V
CC
inputs are met, as specified in the
Spartan-6 FPGA Data Sheet. Similarly, this is also true if V
CCO
and V
CCINT
are being
considered for combination, when using a 1.2V V
CCO
. The supplies for the GTP transceiver
V
CC
pins should never be combined with other rails on the board.
Time Delay
Distance from the FPGA power pins to the capacitor
Signal propagation speed through FR4 dielectric
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