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Xilinx Spartan-6 FPGA Series User Manual

Xilinx Spartan-6 FPGA Series
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Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 43
UG393 (v1.1) April 29, 2010
Traces
Traces
Trace Geometry
For any trace, its characteristic impedance is dependent on its stackup geometry as well as
the trace geometry. In the case of differential traces, the inductive and capacitive coupling
between the tightly coupled pair also determines the characteristic impedance of the
traces.
The impedance of a trace is determined by its inductive and capacitive coupling to nearby
conductors. For example, these conductors can be planes, vias, pads, connectors, and other
traces, including the other closely coupled trace in a differential pair. The substrate
properties, conductor properties, flux linkage area, and distance to a nearby conductor
determine the amount of coupling and hence, the contribution to the final impedance.
2D field solvers are necessary in resolving these complex interactions and contribute to the
calculation of the final impedance of the trace. They are also a useful tool to verify existing
trace geometries.
Wider traces create a larger cross-sectional area for current to flow and reduce resistive
losses in high-speed interfaces. Use the widest traces that space constraints allow. Because
trace width tolerances are expressed in absolute terms, a wider trace also minimizes the
percentage variation of the manufactured trace, resulting in tighter impedance control
along the length of the transmission line.
Sometimes, striplines are preferred over microstrips because the reference planes on both
sides of the trace provide radiation shielding. Microstrips are shielded on only one side (by
the reference plane) because they run on the top-most or bottom-most layers, leaving the
other side exposed to the environment.
For best results, the use of a 2D or 3D field solver is recommended for verification.
Trace Characteristic Impedance Design for High-Speed Transceivers
Because the transceivers use differential signaling, the most useful trace configurations are
differential edge-coupled stripline and differential microstrip. While some backplanes use
the differential broadside-coupled stripline configuration, it is not recommended for
10 Gb/s operation, because the P and N vias are asymmetrical and introduce common-
mode non-idealities.
With few exceptions, 50Ω characteristic impedance (Z
0
) is used for transmission lines in
the channel. In general, when the width/spacing (W/S) ratio is greater than 0.4 (8 mil wide
traces with 20 mil separation), coupling between the P and N signals affects the trace
impedance. In this case, the differential traces must be designed to have an odd mode
impedance (Z
0O
) of 50Ω , resulting in a differential impedance (Z
DIFF
) of 100Ω , because
Z
DIFF
=2xZ
0O
.
The same W/S ratio also must be less than 0.8, otherwise strong coupling between the
traces requires narrower, lossier traces for a Z
0O
of 50Ω. To clarify, with Z
0O
at 50Ω, an even
mode impedance (Z
0E
) of 60Ω or below is desired.
Figure 4-1 through Figure 4-4 show example cross sections of differential structures.

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Xilinx Spartan-6 FPGA Series Specifications

General IconGeneral
Device FamilySpartan-6
CategoryFPGA
Number of Logic Cells3, 840 to 147, 443
Block RAM216 Kb to 4, 824 Kb
Maximum User I/O102 to 576
Process Technology45nm
Operating Voltage1.2V
Number of DSP Slices8 to 180
Package OptionsFG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156

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