Xilinx Spartan-6 FPGA Series User Manual

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Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 37

UG393 (v1.1) April 29, 2010

Troubleshooting

Optimum Decoupling Network Design

If a highly optimized PDS is needed, measurements and simulations of a prototype system

can inform the PDS design. Using knowledge of the noise spectrum generated by the

prototype system along with knowledge of the system’s power system impedance, the

unique transient current of the design can be determined and accommodated.

To measure the noise spectrum of the design under operating conditions, use either a

spectrum analyzer or an oscilloscope with FFT. The power system impedance can be

determined either through direct measurement or simulation, or a combination of these

two as there are often many variables and unknowns.

Both the noise spectrum and the impedance are functions of frequency. By examining the

quotient of these per frequency point, transient current as a function of frequency is

computed (Equation 2-7):

Equation 2-7

Using the data sheet’s maximum voltage ripple value, the impedance value needed at all

frequencies can be determined. This yields a target impedance as a function of frequency.

A specially designed capacitor network can accommodate the specific design’s transient

current.

Troubleshooting

In some cases the proper design work is done up-front, but noise problems still exist. This

next section describes possible issues and suggested resolution methods.

Possibility 1: Excessive Noise from Other Devices on the PCB

Sometimes ground and/or power planes are shared among many devices, and noise from

an inadequately decoupled device affects the PDS at other devices. Common causes of this

noise are:

• RAM interfaces with inherently high-transient current demands resulting either from

temporary periodic contention or high-current drivers

• Large ASICs

When unacceptable amounts of noise are measured locally at these devices, the local PDS

and the component decoupling networks should be analyzed.

Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces

Sometimes the decoupling network capacitance is adequate, but there is too much

inductance in the path from the capacitors to the FPGA.

Possible causes are:

• Wrong decoupling capacitor connecting-trace geometry or solder-land geometry

• The path from the capacitors to the FPGA is too long

- and/or -

• A current path in the power vias traverses an exceptionally thick PCB stackup.

For inadequate connecting trace geometry and capacitor land geometry, review the loop

inductance of the current path. If the vias for a decoupling capacitor are spaced a few

If()

Vf()From Spectrum Analyzer

Zf()From Network Analyzer

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Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156