Xilinx Spartan-6 FPGA Series User Manual

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38 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning

UG393 (v1.1) April 29, 2010

Chapter 2: Power Distribution System

millimeters from the capacitor solder lands on the board, the current loop area is greater

than necessary (see Figure 2-1A).

To reduce the current loop area, vias should be placed directly against capacitor solder

lands (see Figure 2-1B). Never connect vias to the lands with a section of trace (see

Figure 2-1A).

Other improvements of geometry are via-in-pad (via under the solder land), not shown,

and via-beside-pad (vias straddle the lands instead of being placed at the ends of the

lands), shown in Figure 2-1C. Double vias also improve connecting trace geometry and

capacitor land geometry (see Figure 2-1D).

Exceptionally thick boards (> 2.3 mm or 90 mils) have vias with higher parasitic

inductance.

To reduce the parasitic inductance, move critical V

/GND plane sandwiches close to the

top surface where the FPGA is located, and place the highest frequency capacitors on the

top surface where the FPGA is located.

Possibility 3: I/O Signals in PCB are Stronger Than Necessary

If noise in the V

CCO

PDS is still too high after refining the PDS, the I/O interface slew rate

can be reduced. This applies to both outputs from the FPGA and inputs to the FPGA. In

severe cases, excessive overshoot on inputs to the FPGA can reverse-bias the IOB clamp

diodes, injecting current into the V

CCO

PDS.

If large amounts of noise are present on V

CCO

, the drive strength of these interfaces should

be decreased, or different termination should be used (on input or output paths).

Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths

I/O signal return currents can also cause excessive noise in the PDS. For every signal

transmitted by a device into the PCB (and eventually into another device), there is an equal

and opposite current flowing from the PCB into the device's power/ground system. If a

low-impedance return current path is not available, a less optimal, higher impedance path

is used. When I/O signal return currents flow over a less optimal path, voltage changes are

induced in the PDS, and the signal can be corrupted by crosstalk. This can be improved by

ensuring every signal has a closely spaced and fully intact return path.

Methods to correct a sub-optimal return current path:

• Restrict signals to fewer routing layers with verified continuous return current paths.

• Provide low-impedance paths for AC currents to travel between reference planes

(decoupling capacitors at PCB locations where layer transitions occur).

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Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156