Xilinx Spartan-6 FPGA Series User Manual

12 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Chapter 1: PCB Technology Basics
dielectric constant of the material in the space around the signal trace and between the
signal trace and the reference plane.
The dielectric constant of the material in the vicinity of the trace and reference plane is a
property of the PCB laminate materials, and in the case of surface traces, a property of the
air or fluid surrounding the board. PCB laminate is typically a variant of FR4, though it can
also be an exotic material.
While the dielectric constant of the laminate varies from board to board, it is fairly constant
within one board. Therefore, the relative impedance of transmission lines in a PCB is
defined most strongly by the trace geometries and tolerances. Impedance variance can
occur based on the presence or absence of glass in a local portion of the laminate weave,
but this rarely poses issues except in high-speed (>6 Gb/s) interfaces.
Return Currents
An often neglected aspect of transmission lines and their signal integrity is return current.
It is incorrect to assume that a signal trace by itself forms a transmission line. Currents
flowing in a signal trace have an equal and opposite complimentary current flowing in the
reference plane beneath them. The relationship of the trace voltage and trace current to
reference plane voltage and reference plane current defines the characteristic impedance of
the transmission line formed by the trace and reference plane. While interruption of
reference plane continuity beneath a trace is not as dramatic in effect as severing the signal
trace, the performance of the transmission line and any devices sharing the reference plane
is affected.
It is important to pay attention to reference plane continuity and return current paths.
Interruptions of reference plane continuity, such as holes, slots, or isolation splits, cause
significant impedance discontinuities in the signal traces. They can also be a significant
source of crosstalk and contributor to Power Distribution System (PDS) noise. The
importance of return current paths cannot be underestimated.

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156

Summary

Chapter 1: PCB Technology Basics

Transmission Lines

Explains the principles of signal transmission over traces and reference planes.

Chapter 2: Power Distribution System

PCB Decoupling Capacitors

Covers capacitor selection, placement, and guidelines for PDS.

Capacitor Specifications

Details electrical characteristics of PCB capacitors and substitution guidelines.

Capacitor Consolidation Rules

PCB Capacitor Placement and Mounting Techniques

Offers guidelines for optimizing capacitor placement and mounting for low inductance.

0805 Ceramic Capacitor

Details placement and mounting geometries for 4.7 µF capacitors.

0402 Ceramic Capacitor

Details placement and mounting geometries for 0.47 µF capacitors.

Basic PDS Principles

Explains PDS concepts like noise limits, voltage variance, and component roles.

Capacitor Placement Background

VREF Stabilization Capacitors

Simulation Methods

Discusses techniques and tools for predicting PDS performance.

PDS Measurements

Describes methods for measuring PDS noise magnitude and spectrum.

Noise Spectrum Measurements

Explains using spectrum analyzers or FFT for determining noise frequencies.

Optimum Decoupling Network Design

Describes using measurements and simulations to optimize PDS design.

Troubleshooting

Addresses common PDS noise issues and suggested resolution methods.

Possibility 1: Excessive Noise from Other Devices on the PCB

Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces

Possibility 3: I/O Signals in PCB are Stronger Than Necessary

Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths

Chapter 3: SelectIO Signaling

Interface Types

Single-Ended Signaling

Chapter 4: PCB Materials and Traces

Dielectric Losses

Choosing the Substrate Material

Traces

Details trace geometry, routing, and characteristic impedance for high-speed signals.

Trace Routing

Chapter 5: Design of Transitions for High-Speed Signals

Excess Capacitance and Inductance

Time Domain Reflectometry

Explains TDR techniques for identifying excess capacitance or inductance in transitions.

BGA Package

SMT Pads

Differential Vias

Microstrip/Stripline Bends

Chapter 6: I/O Pin and Clock Planning

Configuration Modes

Guidelines for pin planning multi-function configuration pins to avoid conflicts.

Memory Controller Block

Covers pin planning considerations for the Memory Controller Block (MCB).

MCB Clocking Considerations

PCI

GTP Transceivers

Pin planning considerations for GTP transceivers, including REFCLK connections.

PCI Express

Advises on defining pin placement for PCI Express before other IP.

Global and I/O Clocking

Guides on selecting clock structures and ensuring buffer availability.

BUFIO2 I/O Clock Buffer Usage

Serializing Interfaces

I/O Standards and I/O Banking Rules

Defines I/O standards, attributes, and banking rules for pin assignments.

Simultaneous Switching Output (SSO) Management

Running Design Rule Checks

Explains using DRCs in software tools to validate clocking and pin assignments.