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Xilinx Spartan-6 FPGA Series User Manual

Xilinx Spartan-6 FPGA Series
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Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 45
UG393 (v1.1) April 29, 2010
Traces
Trace Routing
High-speed serial differential traces are routed with the highest priority to ensure that the
optimal path is available to these critical traces. This reduces the need for bends and vias
and minimizes the potential for impedance transitions. Traces must be kept straight, short,
and with as few layer changes as possible. The impact of vias is discussed in Differential
Vias, page 53.
Routing of high-speed traces must be avoided near other traces or other potential sources
of noise. Traces on neighboring signal planes should run perpendicular to minimize
crosstalk.
Striplines are to be used whenever possible, as are the uppermost and lowermost stripline
layers to minimize via stubs. When the stackup is being planned, these layers must be
placed as close to the top and bottom layers whenever possible.
Design constraints might require microstrips for the BGA exit path or from via to
connector launch or SMT pads. In such cases, the microstrip trace must be kept as short as
possible.
Mitered 45-degree bends are recommended (as opposed to 90-degree bends). At a
90-degree bend, the effective width of the trace changes, causing an impedance
discontinuity due to the capacitive coupling of the additional conductor area to the
reference plane.
The two traces of a differential pair must be length-matched to eliminate skew. Skew
creates mismatches in the common mode and reduces the differential voltage swing as a
result.
Plane Splits
Ground planes should be used as reference planes for signals, as opposed to noisier power
planes. Each reference plane should be contiguous for the length of the trace, because
routing over plane splits creates an impedance discontinuity. In this case, the impedance of
the trace changes because its coupling to the reference plane is changed abruptly at the
plane split.
Return Currents
Routing over plane splits also creates issues with the return current. High-speed signals
travel near the surface of the trace due to the skin effect mentioned in Dielectric Losses,
page 41. Meanwhile, the return current also travels near the surface of the tightly coupled
reference plane.
Because of the tight coupling, the return current has the tendency to travel close to the
original signal-carrying trace. At the plane split, the return current can no longer follow the
same path parallel to the trace, but must instead find an alternative route.
A plane split causes a suboptimal current return path and increases the current loop area,
thereby increasing the inductance of the trace at the plane split, changing the impedance of
the trace.

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Xilinx Spartan-6 FPGA Series Specifications

General IconGeneral
Device FamilySpartan-6
CategoryFPGA
Number of Logic Cells3, 840 to 147, 443
Block RAM216 Kb to 4, 824 Kb
Maximum User I/O102 to 576
Process Technology45nm
Operating Voltage1.2V
Number of DSP Slices8 to 180
Package OptionsFG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156

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