64 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Chapter 6: I/O Pin and Clock Planning
GTP Transceiver Clocking Considerations
GTP transceivers use BUFIO2 clock buffers to reach the DCM, PLL, and BUFG resources
for FPGA logic clocking. From one to all eight BUFIO2s on a side can be used by the GTP
transceivers. Monitoring how many specific BUFIO2s are used ensures that the desired
pinout does not require more BUFIO2s than are available. The SelectIO interfaces and the
GCLK pin to DCM/PLL connectivity also compete for the same BUFIO2 clock buffers as
the GTP transceivers. This is described in the BUFIO2 I/O Clock Buffer Usage section.
The connectivity between the GTP transceiver output clocks and BUFIO2 is described in
Chapter 1 of the Spartan-6 FPGA Clocking Resources User Guide.
PCI Express
The best designs define the pin placement and GTP transceiver usage with the integrated
block for PCI Express® before any other GTP transceiver based IP is planned. To ensure
proper timing, the integrated block for PCI Express uses the closest GTP transceivers.
Both the Core Generator tool and the Spartan-6 FPGA Integrated Endpoint Block for PCI
Express User Guide are helpful when defining the pin placement and GTP transceiver
usage. The integrated block for PCI Express only allows using the GTP transceivers on the
top half of the device. The supported GTP transceiver locations are described in a table in
the Supported Core Pinouts section (Chapter 7) of the Spartan-6 FPGA Integrated Endpoint
Block for PCI Express User Guide.
Other GTP Transceiver Based Tools
To support the desired core, and ensure enough GTP transceivers are available, use the
Core Generator tool to generate valid pin placements for Xilinx provided cores. Multi-lane
cores require adjacent GTP transceivers.
Global and I/O Clocking
Defining the best clocking structure for a design is an important aspect of pin planning.
Before locking the pin placement, the designer must make sure that the design does not
require more clock buffers or clock I/O pins than are available in any given region, and
that the connectivity is valid. For simple designs, those with only a few I/O, global, or GTP
transceiver derived clocks, this determination can be accomplished using the guidelines in
this chapter. For designs with a high utilization of clock resources in any given region, the
I/O interfaces, clock structures, and any IP required specific clock buffers should be
entered into the design and run through the ISE software. The ISE software provides the
design rule checks (DRCs) for valid clock usage and I/O pin assignments.
GCLK Pin Assignment
The memory controller blocks, the PCI core interfaces, and the 16-bit wide configuration
modes all share multi-function pins with GCLKs. The availability of GCLK pins for a given
package should be checked to ensure that the pins are not needed for other shared
functions.
The clock column in the PlanAhead Package Pins view can group all the GCLK pins in a
single list by deselecting the Group by I/O Bank icon on the left, and then using the clock
header to sort the column.
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