Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 65
UG393 (v1.1) April 29, 2010
Global and I/O Clocking
A GCLK pin to BUFG connectivity check will ensure that there are no GCLK pin
assignment conflicts for the same BUFG global clock line. See the Shared Global Clocking
Resources tables (Chapter 1) of the Spartan-6 FPGA Clocking Resources User Guide for more
details. The 16 GCLK pins in I/O banks 0 and 1 share the same eight BUFG buffers. The 16
GCLK pins in I/O banks 2 and 3 share the same eight BUFG buffers.
The GCLK pins that are intended to drive DCMs or PLLs must have the required BUFIO2
available to connect them. The GCLK pin to BUFIO2 connectivity is shown in the BUFIO2
Input Conflicts for SDR Data Rates and BUFIO2 Input Conflicts for DDR Data Rates tables
(Chapter 1) of the Spartan-6 FPGA Clocking Resources User Guide.
BUFIO2s (and therefore the high-speed connections from their GCLK pins) on the top half
of the device (BUFIO2 regions TL, TR, LT, and RT) can connect to the clock management
tiles (CMTs) in the top half of the device; BUFIO2s on the bottom half (BUFIO2 regions BL,
BR, LB, and RB) can connect to CMTs on the bottom half of the device. This connectivity is
important when a clock needs to drive multiple PLLs, or when both BUFIO2s and CMTs
are being floorplanned, or when the design over-utilizes BUFIO2 resources on one side of
the device.
When assigning differential clock inputs, always ensure the master side of the clock is
assigned to the P side of the differential clock pin pair, and the slave side of the clock to the
N side.
BUFIO2 I/O Clock Buffer Usage
Each side of the Spartan-6 device (top, bottom, left, and right) has two BUFIO2 clock
regions. There are four BUFIO2 clock buffers available per clock region. Therefore, each
side of the device has eight BUFIO2 clock buffers. For the smaller device/package
combinations, a side encompasses only one I/O bank (banks 0, 1, 2, and 3). However, on
some larger device/package combinations there are additional I/O banks 4 and 5. The
devices with banks 1 and 5 share the clock resources on the right side, and banks 3 and 4
share the clock resources on the left side. Within each BUFIO2 clock region, there are three
competing uses for the BUFIO2 clock buffers: high-speed I/O clocks, GCLK pin
connectivity to the DCMs and PLLs, and GTP clock connectivity to the DCMs, PLLs, and
BUFGs. These three competing uses must be balanced when defining pin assignments,
requiring no more than four buffers per BUFIO2 clock region.
It is important to ensure that a design will require no more than four BUFIO2 clock buffers
per BUFIO2 clock region. Each BUFIO2 clock region contains enough routing resources to
support up to eight clocks total (including clocks driven by BUFIO2 buffers, as well as
other clock buffers).
Four I/O clocks can be driven by BUFIO2 clock buffers, each limited to that single BUFIO2
clock region. Xilinx recommends keeping the BUFIO2 driven interfaces to a single BUFIO2
clock region to conserve BUFIO2 clock buffers. Splitting a single interface across two
BUFIO2 clock regions requires two BUFIO2 clock buffers; in contrast, the same interface
within a single BUFIO2 clock region only requires one BUFIO2 buffer.
When two I/O clocks are driven by a BUFPLL, each spans the two BUFIO2 clock regions
on a side.
There are two global clocks that can be driven from any of the 16 global clock lines.
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