Xilinx Spartan-6 FPGA Series User Manual

40 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Chapter 3: SelectIO Signaling
is higher than the voltage of the P signal, the state is considered Low. Typically the P and N
signals have similar swing, and have a common-mode voltage above GND (although this
is not always the case). LVDS is one common example of a differential I/O standard.
SDR versus DDR Interfaces
The difference between Single Data Rate (SDR) and Double Data Rate (DDR) interfaces has
to do with the relationship of the data signals of a bus to the clock signal of that bus. In SDR
systems, data is only registered at the input flip-flops of a receiving device on either the
rising or the falling edge of the clock. One full clock period is equivalent to one bit time. In
DDR systems, data is registered at the input flip-flops of a receiving device on both the
rising and falling edges of the clock. One full clock period is equivalent to two bit times.
The distinction of SDR and DDR has nothing to do with whether the I/O standard carrying
the signals is single-ended or differential. A single-ended interface can be SDR or DDR,
and a differential interface can also be SDR or DDR.
Single-Ended Signaling
A variety of single-ended I/O standards are available in the Spartan-6 FPGA IOB
configuration options.
Modes and Attributes
Some of these I/O standards can be used only in unidirectional mode, while some can be
used in bidirectional mode or unidirectional mode.
Some I/O standards have attributes to control drive strength and slew rate, as well as the
presence of weak pull-up or pull-down, and weak-keeper circuits (not intended for use as
parallel termination), and stronger input-termination resistors. Drive strength, slew rate,
and in some cases specifying untuned output driver impedance can be used to tune an
interface for adequate speed while not overdriving the signals. Weak pull-ups, weak pull-
downs, and weak keepers can be used to ensure a known or steady level on a floating or 3-
stated signal. See the Spartan-6 FPGA SelectIO Resources User Guide for more information.
Input Thresholds
The input circuitry of the single-ended standards fall into two categories: those with fixed
input thresholds and those with input thresholds set by the V
REF
voltage. The use of V
REF
has three advantages:
• It allows for tighter control of input threshold levels
• It removes dependence on die GND for the threshold reference
• It allows for input thresholds to be closer together, which reduces the need for a large
voltage swing of the signal at the input receiver
Two 1.8V I/O standards that illustrate this are LVCMOS18 and SSTL18 Class 1. When a
Spartan-6 FPGA is receiving, the input thresholds, V
IL
and V
IH
, are much closer together
for the SSTL18 standard.
This smaller required swing allows for higher frequency of operation in the overall link. A
smaller swing at the driver means reduced DC power is required with less transient
current. The one drawback to the use of V
REF
is that the semi-dedicated V
REF
pins of the
bank cannot be used as I/Os – they must all be connected to an external reference voltage
with a decoupling capacitor for each V
REF
pin. For more information on V
REF
decoupling
and decoupling of all other supplies, see Chapter 2, Power Distribution System.

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156