Xilinx Spartan-6 FPGA Series User Manual

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 13
UG393 (v1.1) April 29, 2010
Chapter 2
Power Distribution System
This chapter documents the power distribution system (PDS) for Spartan®-6 FPGAs,
including decoupling capacitor selection, placement, and PCB geometries. A simple
decoupling method is provided for each device in the Spartan-6 family. Basic PDS design
principles are covered, as well as simulation and analysis methods. This chapter contains
the following sections:
• PCB Decoupling Capacitors
• Basic PDS Principles
• Simulation Methods
• PDS Measurements
• Troubleshooting
PCB Decoupling Capacitors
Recommended Capacitors per Device
A simple PCB-decoupling network for each Spartan-6 device is listed in Table 2-1.
Decoupling methods other than those presented in Table 2-1 can be used, but the
decoupling network should be designed to meet or exceed the performance of the simple
decoupling networks presented here. The impedance of the alternate network must be less
than or equal to that of the recommended network across frequencies from 100 KHz to
500 MHz.
Because device capacitance requirements vary with CLB and I/O utilization, PCB
decoupling guidelines are provided on a per-device basis. V
CCINT
and V
CCAUX
capacitors
are listed as the quantity per device, while V
CCO
capacitors are listed as the quantity per
I/O bank. Device performance at full utilization is equivalent across all devices when
using these recommended networks.

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156