Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 27
UG393 (v1.1) April 29, 2010
Basic PDS Principles
the two opposing paths reduces the loop’s total inductance. Therefore, when given a
choice, V
CC
and GND vias should be as close together as possible.
The via field under an FPGA has many V
CC
and GND vias, and the total inductance is a
function of the proximity of one via to another:
•For core V
CC
supplies (V
CCINT
and V
CCAUX
), opposing current is between the V
CC
and GND pins.
•For I/O V
CC
supplies (V
CCO
), opposing current is between any I/O and its return
current path, whether carried by a V
CCO
or GND pin.
To reduce parasitic inductance:
•V
CCINT
and GND are placed in a checkerboard arrangement in the center area of the
BGA packages.
•V
CCO
and GND pins are distributed among the I/O pins.
In BGA packages, FPGA pinout arrangement determines the PCB via arrangement. The
PCB designer cannot control the proximity of opposing current paths but has control over
the trade-offs between the capacitor’s mounting inductance and FPGA’s mounting
inductance:
• Both mounting inductances are reduced by placing power planes close to the PCB
stackup’s top half and placing the capacitors on the top surface (reducing the
capacitor’s via length).
• If power planes are placed in the PCB stackup’s bottom half, the capacitors must be
mounted on the PCB backside. In this case, FPGA mounting vias are already long, and
making the capacitor vias long (by coming down from the top surface) is a bad
practice. A better practice is to take advantage of the short distance between the
underside of the PCB and the power plane of interest, mounting capacitors on the
underside.
PCB Stackup and Layer Order
V
CC
and ground plane placement in the PCB stackup (the layer order) has a significant
impact on the parasitic inductances of power current paths. Layer order must be
considered early in the design process:
• High-priority supplies should be placed closer to the FPGA (in the PCB stackup’s top
half)
• Low-priority supplies should be placed farther from the FPGA (in the PCB stackup’s
bottom half)
Power supplies with high transient current should have the associated V
CC
planes close to
the top surface (FPGA side) of the PCB stackup. This decreases the vertical distance (V
CC
and GND via length) that currents travel before reaching the associated V
CC
and GND
planes. To reduce spreading inductance, every V
CC
plane should have an adjacent GND
plane in the PCB stackup. The skin effect causes high-frequency currents to couple tightly,
and the GND plane adjacent to a specific V
CC
plane tends to carry the majority of the
current complementary to that in the V
CC
plane. Thus, adjacent V
CC
and GND planes are
treated as a pair.
Not all V
CC
and GND plane pairs reside in the PCB stackup’s top half because
manufacturing constraints typically require a symmetrical PCB stackup around the center
(with respect to dielectric thicknesses and etched copper areas). The PCB designer chooses
the priority of the V
CC
and GND plane pairs: high priority pairs carry high transient
To Next Page
Loading...
Need help?
General
