Xilinx Spartan-6 FPGA Series User Manual

68 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Chapter 6: I/O Pin and Clock Planning
of routing through the device (from inputs, to internal logic, to outputs). See WP311:
Improving Performance in Spartan-6 FPGA Designs for a discussion on this topic.
Density Migration
When migrating a design to a different density in the same package, it is important to
ensure that the pins selected during the pin-planning process are available across the
available devices. Chapter 7 of the Spartan-6 FPGA Packaging and Pinouts Specification
provides more details on density migration.

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156