Xilinx Spartan-6 FPGA Series User Manual

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 53
UG393 (v1.1) April 29, 2010
Differential Vias
Differential Vias
The most common transition is the differential via where the signal pair must transition
from an upper stripline layer or top microstrip to a lower stripline layer or bottom
microstrip.
Figure 5-13 shows a Ground-Signal-Signal-Ground (GSSG) type differential via. Ground
vias are connected to each ground plane in the stackup, while signal layers only contain
pads for the entry and exit layers.
X-Ref Target - Figure 5-11
Figure 5-11: 840 fF Excess Capacitance with Ground Plane Intact
X-Ref Target - Figure 5-12
Figure 5-12: 57 fF Excess Capacitance with Ground Plane Intact
550
500
450
400
350
300
0.55 0.60 0.65 0.70 0.80 0.90 0.95 1.000.850.75
Time, ns
m1
VtdrPlaneNotCleared, mV
VtdrPlaneCleared, mV
UG393_c5_11_091809
m2
550
500
450
400
350
300
0.55 0.60 0.65 0.70 0.80 0.90 0.95 1.000.850.75
Time, ns
m1
VtdrPlaneNotCleared, mV
VtdrPlaneCleared, mV
UG393_c5_12_091809
m2

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156