Xilinx Spartan-6 FPGA Series User Manual

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 61
UG393 (v1.1) April 29, 2010
Chapter 6
I/O Pin and Clock Planning
This chapter contains guidelines for pin-planning and clocking considerations when
designing with Spartan-6 FPGAs. Choosing the correct resources enables a faster and
cleaner design process. Xilinx recommends using the ISE® software PlanAhead tool to
select the pins for the design. Follow these guidelines to avoid board layout, pin
assignment, and FPGA resource conflicts. Using these guidelines also provides confidence
in initial design pin assignments. After following these guidelines for the I/O and clock
structures, run the design through the ISE software for a final check against the design
rules for possible warnings or errors.
Configuration Modes
Configuration Pin Planning Considerations
The best designs remove any possibility of signal contention on the multi-function
configuration pins during configuration. The simplest method is to prohibit the
multi-function configuration pins from being used as user I/O, this is only possible when
there is enough available I/O for the design.
The Package Pins view in the PlanAhead tool lists all the dedicated and multi-function
pins for the selected configuration mode. The Spartan-6 FPGA Configuration Guide can be
used to identify the pins used in each mode.
Multi-function Configuration
The multi-function configuration pins must be examined for overlaps with other design
functionality requirements.
GCLK
In x16 configuration modes, D13, D14, and D15 of the upper data bus uses the same I/O as
the GCLK inputs. Since clock signals are typically not easy to 3-state during configuration,
most designs must account for three fewer GCLK pins when using the x16 modes.
V
REF
Pins, and BPI and SelectMAP Configuration Modes
In bank 2, the Slave SelectMAP configuration mode requires the use of the RDWR pin,
which also doubles as a V
REF
pin. Therefore, a design cannot include I/O standards that
require V
REF
in bank 2 (such as SSTL or HSTL) while using the Slave SelectMap
configuration mode. Designers need to review the tradeoffs before dedicating
multi-function pins.
Similarly, in bank 1 the BPI configuration mode requires the use of some multi-function
pins that also serve as V
REF
pins. Therefore, designs cannot include both I/O standards

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156