66 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Chapter 6: I/O Pin and Clock Planning
Overview of BUFIO2 Resource Usage per Interface Type
• Each single-ended SDR interface consumes one BUFIO2 buffer.
• Each single-ended DDR interface consumes two BUFIO2 buffers.
• Each differential interface requires two BUFIO2 buffers.
• Each GCLK clock input to the DCM or PLL connections use one BUFIO2 buffer.
• Each GTP transceiver clock used to clock the FPGA logic resources uses one BUFIO2
buffer.
Bidirectional I/O
Valid clock buffer combinations for bidirectional I/O are further described in the Possible
Clock Structures for Bidirectional I/O table (Chapter 2) in the Spartan-6 FPGA SelectIO
Resources User Guide.
Ensure that each of the four BUFIO2 clock buffers per BUFIO2 clock region can be driven
from the desired GCLK input or a GTP transceiver. The GCLK and GTP-to-BUFIO2
connectivity is shown in the BUFIO2 Input Conflicts for SDR Data Rates and BUFIO2 Input
Conflicts for DDR Data Rates tables (Chapter 1) in the Spartan-6 FPGA Clocking Resources
User Guide.
Any BUFIO2 clocked interfaces using the IODELAY2 clock delay adjustment must be
limited to a single BUFIO2 clock region. The IODELAY2 primitive is limited to a single
fanout GCLK-to-BUFIO2 connection, and cannot support the GCLK to two BUFIO2s
connection required for interfaces that span two BUFIO2 regions.
Serializing Interfaces
The SelectIO wizard (in the ISE software) is used to create the proper I/O and clocking
structure. The Spartan-6 FPGA I/Os include many innovations not available in previous
Spartan FPGA generations. Serialized I/O interfaces must be designed specifically for the
latest devices. See X
APP1064, Source-Synchronous Serialization and Deserialization (up to 1050
Mb/s) for detailed examples of different I/O interfaces.
Pin Planning Considerations
Single-Ended SerDes
Single-ended I/O can be serialized (4:1) on any given I/O. For serializations of greater than
4:1, multiple input pins are cascaded. Cascades must always start with a P pin.
Serialization will consume the SerDes and the appropriate input or output register of the
associated N pin. The N pin can still be used as an unrelated I/O, minus the SerDes and
associated input or output register.
Examples
• An 8-bit, 4:1 SerDes uses eight I/O, or four P/N pairs.
• An 8-bit, 8:1 SerDes uses eight P pins to start each of the eight SerDes, plus the eight
associated N pins for the second half of the two cascaded 4:1 SerDes.
The N pins can still be used for unrelated I/O, as long as they do not use a SerDes.
However, these other signals must be interleaved with the SerDes bus for board routing.
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